From 8edca81ece5df534c1cdd1f8362e7b5b9b090cfa Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Mon, 9 Nov 2020 11:09:12 +0000 Subject: [PATCH] aarch64: Limit Rt register number for LS64 load/store instructions Atomic 64-byte load/store instructions limit Rt register number to values matching below condition (register number must be even and <= 22): if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; This patch adds check if Rt fulfills above requirement. For more details regarding atomic 64-byte load/store instruction for Armv8.7 please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document page 157 for load instruction, and pages 414-418 for store instructions of [0]. [0]: https://developer.arm.com/docs/ddi0596/i --- gas/ChangeLog | 8 ++ gas/config/tc-aarch64.c | 16 +++ gas/testsuite/gas/aarch64/ls64-invalid.l | 80 ++++++++++- gas/testsuite/gas/aarch64/ls64-invalid.s | 131 +++++++++++++++++- gas/testsuite/gas/aarch64/ls64.s | 70 ++++++---- include/ChangeLog | 4 + include/opcode/aarch64.h | 1 + opcodes/ChangeLog | 10 ++ opcodes/aarch64-asm-2.c | 161 ++++++++++----------- opcodes/aarch64-dis-2.c | 169 ++++++++++++----------- opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 1 + opcodes/aarch64-tbl.h | 9 +- 13 files changed, 459 insertions(+), 202 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index f1ba270f682..d14bcc6d031 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2020-11-09 Przemyslaw Wirkus + + * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Rt_LS64. + (parse_operands): Parse Rt range for AARCH64_OPND_Rt_LS64. + * testsuite/gas/aarch64/ls64-invalid.l: Update test. + * testsuite/gas/aarch64/ls64-invalid.s: Update test. + * testsuite/gas/aarch64/ls64.s: Update test. + 2020-11-09 Andreas Schwab * Makefile.am (development.exp): Fix regexp. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 73600e20393..4308ea62663 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5276,6 +5276,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_Rm: case AARCH64_OPND_Rt: case AARCH64_OPND_Rt2: + case AARCH64_OPND_Rt_LS64: case AARCH64_OPND_Rt_SP: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: @@ -5645,10 +5646,25 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_Rt2: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: + case AARCH64_OPND_Rt_LS64: case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: case AARCH64_OPND_SVE_Rm: po_int_reg_or_fail (REG_TYPE_R_Z); + + /* In LS64 load/store instructions Rt register number is . */ + if (operands[i] == AARCH64_OPND_Rt_LS64) + { + /* We've already checked if this is valid register. + This will check if register number (Rt) is not undefined for LS64 + instructions: + if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */ + if ((info->reg.regno & 0x18) == 0x18 || (info->reg.regno & 0x01) == 0x01) + { + set_syntax_error (_("invalid Rt register number in 64-byte load/store")); + goto failure; + } + } break; case AARCH64_OPND_Rd_SP: diff --git a/gas/testsuite/gas/aarch64/ls64-invalid.l b/gas/testsuite/gas/aarch64/ls64-invalid.l index 64b6e58bd64..4ccce6b234d 100644 --- a/gas/testsuite/gas/aarch64/ls64-invalid.l +++ b/gas/testsuite/gas/aarch64/ls64-invalid.l @@ -1,5 +1,77 @@ .*: Assembler messages: -.*: Error: selected processor does not support `ld64b x0,\[x1\]' -.*: Error: selected processor does not support `st64b x0,\[x1\]' -.*: Error: selected processor does not support `st64bv x0,x1,\[x2\]' -.*: Error: selected processor does not support `st64bv0 x0,x1,\[x2\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x1,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x3,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x5,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x7,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x9,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x11,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x13,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x15,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x17,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x19,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x21,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x23,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x24,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x25,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x26,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x27,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x28,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x29,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `ld64b x30,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x1,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x3,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x5,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x7,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x9,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x11,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x13,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x15,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x17,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x19,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x21,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x23,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x24,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x25,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x26,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x27,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x28,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x29,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 1 -- `st64b x30,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x1,\[x2\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x3,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x5,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x7,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x9,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x11,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x13,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x15,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x17,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x19,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x21,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x23,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x24,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x25,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x26,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x27,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x28,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x29,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv x0,x30,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x1,\[x2\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x3,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x5,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x7,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x9,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x11,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x13,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x15,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x17,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x19,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x21,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x23,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x24,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x25,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x26,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x27,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x28,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x29,\[x1\]' +.*: Error: invalid Rt register number in 64-byte load/store at operand 2 -- `st64bv0 x0,x30,\[x1\]' diff --git a/gas/testsuite/gas/aarch64/ls64-invalid.s b/gas/testsuite/gas/aarch64/ls64-invalid.s index 8c89aafc0a8..151fe41c149 100644 --- a/gas/testsuite/gas/aarch64/ls64-invalid.s +++ b/gas/testsuite/gas/aarch64/ls64-invalid.s @@ -1,14 +1,137 @@ -/* Atomic 64-byte load/store instructions require Armv8.7-a extension. */ -.arch armv8.6-a +/* Atomic 64-byte load/store instructions limit register number Rt to below + condition: the register number should be even and <= 22. */ +.arch armv8.7-a+ls64 /* Single-copy Atomic 64-byte Load. */ ld64b x0, [x1] + ld64b x1, [x1] + ld64b x2, [x1] + ld64b x3, [x1] + ld64b x4, [x1] + ld64b x5, [x1] + ld64b x6, [x1] + ld64b x7, [x1] + ld64b x8, [x1] + ld64b x9, [x1] + ld64b x10, [x1] + ld64b x11, [x1] + ld64b x12, [x1] + ld64b x13, [x1] + ld64b x14, [x1] + ld64b x15, [x1] + ld64b x16, [x1] + ld64b x17, [x1] + ld64b x18, [x1] + ld64b x19, [x1] + ld64b x20, [x1] + ld64b x21, [x1] + ld64b x22, [x1] + ld64b x23, [x1] + ld64b x24, [x1] + ld64b x25, [x1] + ld64b x26, [x1] + ld64b x27, [x1] + ld64b x28, [x1] + ld64b x29, [x1] + ld64b x30, [x1] /* Single-copy Atomic 64-byte Store without Return. */ st64b x0, [x1] + st64b x1, [x1] + st64b x2, [x1] + st64b x3, [x1] + st64b x4, [x1] + st64b x5, [x1] + st64b x6, [x1] + st64b x7, [x1] + st64b x8, [x1] + st64b x9, [x1] + st64b x10, [x1] + st64b x11, [x1] + st64b x12, [x1] + st64b x13, [x1] + st64b x14, [x1] + st64b x15, [x1] + st64b x16, [x1] + st64b x17, [x1] + st64b x18, [x1] + st64b x19, [x1] + st64b x20, [x1] + st64b x21, [x1] + st64b x22, [x1] + st64b x23, [x1] + st64b x24, [x1] + st64b x25, [x1] + st64b x26, [x1] + st64b x27, [x1] + st64b x28, [x1] + st64b x29, [x1] + st64b x30, [x1] + /* Single-copy Atomic 64-byte Store with Return. */ - st64bv x0, x1, [x2] + st64bv x1, x0, [x2] + st64bv x0, x1, [x2] + st64bv x0, x2, [x1] + st64bv x0, x3, [x1] + st64bv x0, x4, [x1] + st64bv x0, x5, [x1] + st64bv x0, x6, [x1] + st64bv x0, x7, [x1] + st64bv x0, x8, [x1] + st64bv x0, x9, [x1] + st64bv x0, x10, [x1] + st64bv x0, x11, [x1] + st64bv x0, x12, [x1] + st64bv x0, x13, [x1] + st64bv x0, x14, [x1] + st64bv x0, x15, [x1] + st64bv x0, x16, [x1] + st64bv x0, x17, [x1] + st64bv x0, x18, [x1] + st64bv x0, x19, [x1] + st64bv x0, x20, [x1] + st64bv x0, x21, [x1] + st64bv x0, x22, [x1] + st64bv x0, x23, [x1] + st64bv x0, x24, [x1] + st64bv x0, x25, [x1] + st64bv x0, x26, [x1] + st64bv x0, x27, [x1] + st64bv x0, x28, [x1] + st64bv x0, x29, [x1] + st64bv x0, x30, [x1] + /* Single-copy Atomic 64-byte EL0 Store with Return. */ - st64bv0 x0, x1, [x2] + st64bv0 x1, x0, [x2] + st64bv0 x0, x1, [x2] + st64bv0 x0, x2, [x1] + st64bv0 x0, x3, [x1] + st64bv0 x0, x4, [x1] + st64bv0 x0, x5, [x1] + st64bv0 x0, x6, [x1] + st64bv0 x0, x7, [x1] + st64bv0 x0, x8, [x1] + st64bv0 x0, x9, [x1] + st64bv0 x0, x10, [x1] + st64bv0 x0, x11, [x1] + st64bv0 x0, x12, [x1] + st64bv0 x0, x13, [x1] + st64bv0 x0, x14, [x1] + st64bv0 x0, x15, [x1] + st64bv0 x0, x16, [x1] + st64bv0 x0, x17, [x1] + st64bv0 x0, x18, [x1] + st64bv0 x0, x19, [x1] + st64bv0 x0, x20, [x1] + st64bv0 x0, x21, [x1] + st64bv0 x0, x22, [x1] + st64bv0 x0, x23, [x1] + st64bv0 x0, x24, [x1] + st64bv0 x0, x25, [x1] + st64bv0 x0, x26, [x1] + st64bv0 x0, x27, [x1] + st64bv0 x0, x28, [x1] + st64bv0 x0, x29, [x1] + st64bv0 x0, x30, [x1] diff --git a/gas/testsuite/gas/aarch64/ls64.s b/gas/testsuite/gas/aarch64/ls64.s index efbd0bf23a3..d9219249f67 100644 --- a/gas/testsuite/gas/aarch64/ls64.s +++ b/gas/testsuite/gas/aarch64/ls64.s @@ -3,38 +3,56 @@ /* Single-copy Atomic 64-byte Load. */ ld64b x0, [x1] - ld64b x1, [x2] - ld64b x2, [x4] - ld64b x4, [x8] - ld64b x8, [x16] + ld64b x2, [x1] + ld64b x4, [x1] + ld64b x6, [x1] + ld64b x8, [x1] + ld64b x10, [x1] + ld64b x12, [x1] + ld64b x14, [x1] ld64b x16, [x1] - ld64b x16, [sp] + ld64b x18, [x1] + ld64b x20, [x1] + ld64b x22, [x1] /* Single-copy Atomic 64-byte Store without Return. */ st64b x0, [x1] - st64b x1, [x2] - st64b x2, [x4] - st64b x4, [x8] - st64b x8, [x16] + st64b x2, [x1] + st64b x4, [x1] + st64b x6, [x1] + st64b x8, [x1] + st64b x10, [x1] + st64b x12, [x1] + st64b x14, [x1] st64b x16, [x1] - st64b x16, [sp] + st64b x18, [x1] + st64b x20, [x1] + st64b x22, [x1] /* Single-copy Atomic 64-byte Store with Return. */ - st64bv x0, x1, [x2] - st64bv x1, x2, [x4] - st64bv x2, x4, [x8] - st64bv x4, x8, [x16] - st64bv x8, x16, [x30] - st64bv x16, x30, [x0] - st64bv x30, x1, [x2] - st64bv x30, x1, [sp] + st64bv x1, x0, [x2] + st64bv x0, x2, [x2] + st64bv x0, x4, [x2] + st64bv x0, x6, [x2] + st64bv x0, x8, [x2] + st64bv x0, x10, [x2] + st64bv x0, x12, [x2] + st64bv x0, x14, [x2] + st64bv x0, x16, [x2] + st64bv x0, x18, [x2] + st64bv x0, x20, [x2] + st64bv x0, x22, [x2] /* Single-copy Atomic 64-byte EL0 Store with Return. */ - st64bv0 x0, x1, [x2] - st64bv0 x1, x2, [x4] - st64bv0 x2, x4, [x8] - st64bv0 x4, x8, [x16] - st64bv0 x8, x16, [x30] - st64bv0 x16, x30, [x0] - st64bv0 x30, x1, [x2] - st64bv0 x30, x1, [sp] + st64bv0 x1, x0, [x2] + st64bv0 x0, x2, [x2] + st64bv0 x0, x4, [x2] + st64bv0 x0, x6, [x2] + st64bv0 x0, x8, [x2] + st64bv0 x0, x10, [x2] + st64bv0 x0, x12, [x2] + st64bv0 x0, x14, [x2] + st64bv0 x0, x16, [x2] + st64bv0 x0, x18, [x2] + st64bv0 x0, x20, [x2] + st64bv0 x0, x22, [x2] diff --git a/include/ChangeLog b/include/ChangeLog index 846b3d168e2..5a4f453d2aa 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2020-11-09 Przemyslaw Wirkus + + * opcode/aarch64.h (enum aarch64_opnd): Add new operand AARCH64_OPND_Rt_LS64. + 2020-11-06 Przemyslaw Wirkus * opcode/aarch64.h (AARCH64_FEATURE_PAC): Add new feature. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ffde1ba374d..304c6cb936d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -201,6 +201,7 @@ enum aarch64_opnd AARCH64_OPND_Rm, /* Integer register as source. */ AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ + AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index fb6c79e6299..c90438c1f0d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2020-11-09 Przemyslaw Wirkus + + * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64 + print. + * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with + Rt_ls64 operands. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + 2020-11-06 Przemyslaw Wirkus * aarch64-tbl.h (PAC): Handle for PAC feature. diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 407f893d0c0..b9771154542 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -625,11 +625,11 @@ aarch64_insert_operand (const aarch64_operand *self, case 10: case 11: case 12: - case 16: + case 13: case 17: case 18: case 19: - case 21: + case 20: case 22: case 23: case 24: @@ -639,7 +639,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 28: case 29: case 30: - case 165: + case 31: case 166: case 167: case 168: @@ -649,7 +649,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 172: case 173: case 174: - case 189: + case 175: case 190: case 191: case 192: @@ -658,34 +658,34 @@ aarch64_insert_operand (const aarch64_operand *self, case 195: case 196: case 197: - case 203: - case 206: + case 198: + case 204: + case 207: return aarch64_ins_regno (self, info, code, inst, errors); - case 14: - return aarch64_ins_reg_extended (self, info, code, inst, errors); case 15: + return aarch64_ins_reg_extended (self, info, code, inst, errors); + case 16: return aarch64_ins_reg_shifted (self, info, code, inst, errors); - case 20: + case 21: return aarch64_ins_ft (self, info, code, inst, errors); - case 31: case 32: case 33: case 34: - case 209: - return aarch64_ins_reglane (self, info, code, inst, errors); case 35: - return aarch64_ins_reglist (self, info, code, inst, errors); + case 210: + return aarch64_ins_reglane (self, info, code, inst, errors); case 36: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 37: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 38: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 39: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 40: case 41: case 42: - case 52: + case 43: case 53: case 54: case 55: @@ -702,13 +702,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 66: case 67: case 68: - case 80: + case 69: case 81: case 82: case 83: - case 162: - case 164: - case 181: + case 84: + case 163: + case 165: case 182: case 183: case 184: @@ -716,96 +716,96 @@ aarch64_insert_operand (const aarch64_operand *self, case 186: case 187: case 188: - case 208: + case 189: + case 209: return aarch64_ins_imm (self, info, code, inst, errors); - case 43: case 44: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 45: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 46: case 47: + case 48: return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); - case 51: - case 152: + case 52: + case 153: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 69: - case 160: - return aarch64_ins_limm (self, info, code, inst, errors); case 70: - return aarch64_ins_aimm (self, info, code, inst, errors); + case 161: + return aarch64_ins_limm (self, info, code, inst, errors); case 71: - return aarch64_ins_imm_half (self, info, code, inst, errors); + return aarch64_ins_aimm (self, info, code, inst, errors); case 72: + return aarch64_ins_imm_half (self, info, code, inst, errors); + case 73: return aarch64_ins_fbits (self, info, code, inst, errors); - case 74: case 75: - case 157: - return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 76: - case 156: case 158: - return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 77: + case 157: + case 159: + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 78: + case 79: return aarch64_ins_cond (self, info, code, inst, errors); - case 84: - case 93: - return aarch64_ins_addr_simple (self, info, code, inst, errors); case 85: - return aarch64_ins_addr_regoff (self, info, code, inst, errors); + case 94: + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 86: + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 87: case 88: - case 90: - case 92: - return aarch64_ins_addr_simm (self, info, code, inst, errors); case 89: - return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 91: + case 93: + return aarch64_ins_addr_simm (self, info, code, inst, errors); + case 90: + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); + case 92: return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 94: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 95: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 96: - return aarch64_ins_sysreg (self, info, code, inst, errors); + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 97: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 98: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 99: case 100: case 101: case 102: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 103: - case 105: - return aarch64_ins_barrier (self, info, code, inst, errors); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 104: - return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 106: - return aarch64_ins_prfop (self, info, code, inst, errors); + return aarch64_ins_barrier (self, info, code, inst, errors); + case 105: + return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); case 107: - return aarch64_ins_none (self, info, code, inst, errors); + return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - return aarch64_ins_hint (self, info, code, inst, errors); + return aarch64_ins_none (self, info, code, inst, errors); case 109: + return aarch64_ins_hint (self, info, code, inst, errors); case 110: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 111: + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 112: case 113: case 114: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 115: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 116: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 117: + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 118: case 119: case 120: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 121: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 122: case 123: case 124: @@ -819,8 +819,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 132: case 133: case 134: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 135: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 136: case 137: case 138: @@ -828,52 +828,53 @@ aarch64_insert_operand (const aarch64_operand *self, case 140: case 141: case 142: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 143: + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 144: case 145: case 146: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 147: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 148: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 149: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 150: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 151: + return aarch64_ins_sve_aimm (self, info, code, inst, errors); + case 152: return aarch64_ins_sve_asimm (self, info, code, inst, errors); - case 153: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 154: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 155: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + case 156: return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); - case 159: + case 160: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 161: + case 162: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 163: + case 164: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 175: case 176: case 177: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 178: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 179: case 180: + case 181: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 198: case 199: case 200: case 201: case 202: + case 203: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 204: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 205: - case 207: + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 206: + case 208: return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index ba5cf84d098..f9fa3a616f2 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -23816,14 +23816,14 @@ aarch64_extract_operand (const aarch64_operand *self, case 6: case 7: case 8: - case 10: + case 9: case 11: case 12: - case 16: + case 13: case 17: case 18: case 19: - case 21: + case 20: case 22: case 23: case 24: @@ -23833,7 +23833,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 28: case 29: case 30: - case 165: + case 31: case 166: case 167: case 168: @@ -23843,7 +23843,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 172: case 173: case 174: - case 189: + case 175: case 190: case 191: case 192: @@ -23852,38 +23852,38 @@ aarch64_extract_operand (const aarch64_operand *self, case 195: case 196: case 197: - case 203: - case 206: + case 198: + case 204: + case 207: return aarch64_ext_regno (self, info, code, inst, errors); - case 9: + case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); - case 13: - return aarch64_ext_regno_pair (self, info, code, inst, errors); case 14: - return aarch64_ext_reg_extended (self, info, code, inst, errors); + return aarch64_ext_regno_pair (self, info, code, inst, errors); case 15: + return aarch64_ext_reg_extended (self, info, code, inst, errors); + case 16: return aarch64_ext_reg_shifted (self, info, code, inst, errors); - case 20: + case 21: return aarch64_ext_ft (self, info, code, inst, errors); - case 31: case 32: case 33: case 34: - case 209: - return aarch64_ext_reglane (self, info, code, inst, errors); case 35: - return aarch64_ext_reglist (self, info, code, inst, errors); + case 210: + return aarch64_ext_reglane (self, info, code, inst, errors); case 36: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 37: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 38: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 39: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 40: case 41: case 42: - case 52: + case 43: case 53: case 54: case 55: @@ -23900,14 +23900,14 @@ aarch64_extract_operand (const aarch64_operand *self, case 66: case 67: case 68: - case 79: + case 69: case 80: case 81: case 82: case 83: - case 162: - case 164: - case 181: + case 84: + case 163: + case 165: case 182: case 183: case 184: @@ -23915,98 +23915,98 @@ aarch64_extract_operand (const aarch64_operand *self, case 186: case 187: case 188: - case 208: + case 189: + case 209: return aarch64_ext_imm (self, info, code, inst, errors); - case 43: case 44: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 45: + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 46: case 47: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 48: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 49: return aarch64_ext_shll_imm (self, info, code, inst, errors); - case 51: - case 152: + case 52: + case 153: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 69: - case 160: - return aarch64_ext_limm (self, info, code, inst, errors); case 70: - return aarch64_ext_aimm (self, info, code, inst, errors); + case 161: + return aarch64_ext_limm (self, info, code, inst, errors); case 71: - return aarch64_ext_imm_half (self, info, code, inst, errors); + return aarch64_ext_aimm (self, info, code, inst, errors); case 72: + return aarch64_ext_imm_half (self, info, code, inst, errors); + case 73: return aarch64_ext_fbits (self, info, code, inst, errors); - case 74: case 75: - case 157: - return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 76: - case 156: case 158: - return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 77: + case 157: + case 159: + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 78: + case 79: return aarch64_ext_cond (self, info, code, inst, errors); - case 84: - case 93: - return aarch64_ext_addr_simple (self, info, code, inst, errors); case 85: - return aarch64_ext_addr_regoff (self, info, code, inst, errors); + case 94: + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 86: + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 87: case 88: - case 90: - case 92: - return aarch64_ext_addr_simm (self, info, code, inst, errors); case 89: - return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 91: + case 93: + return aarch64_ext_addr_simm (self, info, code, inst, errors); + case 90: + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); + case 92: return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 94: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 95: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 96: - return aarch64_ext_sysreg (self, info, code, inst, errors); + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 97: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 98: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 99: case 100: case 101: case 102: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 103: - case 105: - return aarch64_ext_barrier (self, info, code, inst, errors); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 104: - return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 106: - return aarch64_ext_prfop (self, info, code, inst, errors); + return aarch64_ext_barrier (self, info, code, inst, errors); + case 105: + return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); case 107: - return aarch64_ext_none (self, info, code, inst, errors); + return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - return aarch64_ext_hint (self, info, code, inst, errors); + return aarch64_ext_none (self, info, code, inst, errors); case 109: + return aarch64_ext_hint (self, info, code, inst, errors); case 110: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 111: + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 112: case 113: case 114: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 115: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 116: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 117: + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 118: case 119: case 120: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 121: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 122: case 123: case 124: @@ -24020,8 +24020,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 132: case 133: case 134: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 135: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 136: case 137: case 138: @@ -24029,52 +24029,53 @@ aarch64_extract_operand (const aarch64_operand *self, case 140: case 141: case 142: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 143: + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 144: case 145: case 146: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 147: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 148: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 149: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 150: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 151: + return aarch64_ext_sve_aimm (self, info, code, inst, errors); + case 152: return aarch64_ext_sve_asimm (self, info, code, inst, errors); - case 153: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 154: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 155: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + case 156: return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); - case 159: + case 160: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 161: + case 162: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 163: + case 164: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 175: case 176: case 177: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 178: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 179: case 180: + case 181: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 198: case 199: case 200: case 201: case 202: + case 203: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 204: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 205: - case 207: + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 206: + case 208: return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index e3d47b4bb5e..f5c67095b99 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -30,6 +30,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 3f142879ed2..67429e97206 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3174,6 +3174,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_Rt2: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: + case AARCH64_OPND_Rt_LS64: case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: case AARCH64_OPND_SVE_Rm: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index f86dde55644..a54b9683919 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3646,10 +3646,10 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0), CORE_INSN ("prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0), /* Atomic 64-byte load/store in Armv8.7. */ - _LS64_INSN ("ld64b", 0xf83fd000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), - _LS64_INSN ("st64b", 0xf83f9000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), - _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), - _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + _LS64_INSN ("ld64b", 0xf83fd000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0), + _LS64_INSN ("st64b", 0xf83f9000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0), + _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0), + _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0), /* Logical (immediate). */ CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF), CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF), @@ -5181,6 +5181,7 @@ struct aarch64_opcode aarch64_opcode_table[] = Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ + Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \ Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \ "an integer or stack pointer register") \ Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ -- 2.30.2