From 8ef241c6f4a976dca67760c43e820d4e812f2fc2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 13:24:28 -0800 Subject: [PATCH] Revert "write_xaiger to not use module POs but only write outputs if driven" This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673. --- backends/aiger/xaiger.cc | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c69b0fa85..5d125b653 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -542,30 +542,18 @@ struct XAigerWriter } for (auto bit : unused_bits) - if (holes_mode) - undriven_bits.erase(bit); - else if (!undriven_bits.count(bit)) - output_bits.insert(bit); - - if (!holes_mode) { - for (auto port : module->ports) { - auto wire = module->wire(port); - if (!wire->port_output) - continue; - for (int i = 0; i < GetSize(wire); i++) { - SigBit wirebit(wire, i); - SigBit bit = sigmap(wirebit); - if (bit == State::Sx) - continue; - if (!undriven_bits.count(bit)) { - output_bits.insert(wirebit); - } - } + undriven_bits.erase(bit); + + if (!undriven_bits.empty() && !holes_mode) { + bool whole_module = module->design->selected_whole_module(module->name); + undriven_bits.sort(); + for (auto bit : undriven_bits) { + if (whole_module) + log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit)); + input_bits.insert(bit); } - - if (!undriven_bits.empty()) - for (auto bit : undriven_bits) - input_bits.insert(bit); + if (whole_module) + log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module)); } if (holes_mode) { -- 2.30.2