From 8ef3d7b1f0e946dbf25e81fa5cf2cbff970ed4af Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Jun 2021 12:47:56 +0100
Subject: [PATCH] add "reverse-gear" mode to mapreduce in SVP64

---
 src/openpower/consts.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index 961929a8..3cc9e08a 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -227,8 +227,10 @@ class SVP64MODEb:
     SZ = 4  # for source
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
+    PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
     SVM = 3  # subvector reduce mode 0=independent 1=horizontal
     CRM = 4  # CR mode on reduce (Rc=1) 0=some 1=all
+    RG = 4   # Reverse-gear on reduce
     # saturation mode
     N = 2  # saturation signed mode 0=signed 1=unsigned
     # ffirst and predicate result modes
-- 
2.30.2