From 8f13581218ad9c20daa1d45618a04c2df4c48b03 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Tue, 8 Feb 2005 21:00:16 +0000 Subject: [PATCH] 2005-02-08 Andrew Cagney * ppc-linux-nat.c (ppc_register_u_addr): Hack around 64-bit PT_FPSCR breakage. --- gdb/ChangeLog | 3 +++ gdb/ppc-linux-nat.c | 15 +++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index f709f7af6e5..248fcdacf37 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,8 @@ 2005-02-08 Andrew Cagney + * ppc-linux-nat.c (ppc_register_u_addr): Hack around 64-bit + PT_FPSCR breakage. + * value.c (struct value): Move to here ... * value.h (struct value): ... from here. Copy comments to corresponding function declarations, re-order. diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index c98bb93f879..9df3e3d126f 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -212,8 +212,19 @@ ppc_register_u_addr (int regno) u_addr = PT_MSR * wordsize; if (tdep->ppc_fpscr_regnum >= 0 && regno == tdep->ppc_fpscr_regnum) - u_addr = PT_FPSCR * wordsize; - + { + /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the + kernel headers incorrectly contained the 32-bit definition of + PT_FPSCR. For the 32-bit definition, floating-point + registers occupy two 32-bit "slots", and the FPSCR lives in + the secondhalf of such a slot-pair (hence +1). For 64-bit, + the FPSCR instead occupies the full 64-bit 2-word-slot and + hence no adjustment is necessary. Hack around this. */ + if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) + u_addr = (48 + 32) * wordsize; + else + u_addr = PT_FPSCR * wordsize; + } return u_addr; } -- 2.30.2