From 8f204e77972e86eb4e1d2475eb4841a74eb1d9a8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Jul 2020 12:50:24 +0200 Subject: [PATCH] sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain. --- litex/boards/targets/nexys4ddr.py | 4 ++-- litex/boards/targets/nexys_video.py | 4 ++-- litex/boards/targets/ulx3s.py | 8 ++++---- litex/soc/integration/soc.py | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 3e7365ed..ea2b62c1 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -30,7 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() - self.clock_domains.cd_sdcard = ClockDomain() + self.clock_domains.cd_sd = ClockDomain() # # # @@ -42,7 +42,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_eth, 50e6) - pll.create_clkout(self.cd_sdcard, 10e6) + pll.create_clkout(self.cd_sd, 10e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index f1e1f274..70a58660 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -30,7 +30,7 @@ class _CRG(Module): self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain() - self.clock_domains.cd_sdcard = ClockDomain() + self.clock_domains.cd_sd = ClockDomain() # # # @@ -42,7 +42,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk100, 100e6) - pll.create_clkout(self.cd_sdcard, 10e6) + pll.create_clkout(self.cd_sd, 10e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 8608aa2b..915eab8e 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -32,7 +32,7 @@ class _CRG(Module): def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) - self.clock_domains.cd_sdcard = ClockDomain() + self.clock_domains.cd_sd = ClockDomain() # # # @@ -46,9 +46,9 @@ class _CRG(Module): pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - pll.create_clkout(self.cd_sdcard, 10e6) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) - self.specials += AsyncResetSynchronizer(self.cd_sdcard, ~pll.locked | rst) + pll.create_clkout(self.cd_sd, 10e6) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) + self.specials += AsyncResetSynchronizer(self.cd_sd, ~pll.locked | rst) # USB PLL if with_usb_pll: diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 667040ba..15cb2b58 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1291,4 +1291,4 @@ class LiteXSoC(SoC): # Timing constraints if not with_emulator: - self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.crg.cd_sdcard.clk) + self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.crg.cd_sd.clk) -- 2.30.2