From 8f3a6f37c953ad1394e8352a1b6fc8e4db3071b9 Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Mon, 22 Apr 2019 21:42:19 -0700 Subject: [PATCH] Update SAC to use new LFSR import --- TLB/src/SetAssociativeCache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py index d23b30cd..965f2e2a 100644 --- a/TLB/src/SetAssociativeCache.py +++ b/TLB/src/SetAssociativeCache.py @@ -20,7 +20,7 @@ from AddressEncoder import AddressEncoder # few bits from it to select which cache line to replace, instead of PLRU # http://bugs.libre-riscv.org/show_bug.cgi?id=71 from plru import PLRU -from LFSR2 import LFSR, LFSR_POLY_24 +from LFSR import LFSR, LFSR_POLY_24 SA_NA = "00" # no action (none) SA_RD = "01" # read -- 2.30.2