From 8f3b5102bb8c1b14aafb9179533914f2a6e920ec Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 16:22:40 +0100 Subject: [PATCH] add pysvp64dis tester --- src/openpower/sv/trans/test_pysvp64dis.py | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 src/openpower/sv/trans/test_pysvp64dis.py diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py new file mode 100644 index 00000000..f25659d2 --- /dev/null +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -0,0 +1,50 @@ +from openpower.simulator.program import Program +from openpower.sv.trans.pysvp64dis import load, dump +from openpower.sv.trans.svp64 import SVP64Asm +import unittest +import sys + +class SVSTATETestCase(unittest.TestCase): + + def test_0_addi(self): + expected = ['addi 1,5,2', + ] + isa = SVP64Asm(expected) + lst = list(isa) + with Program(lst, bigendian=False) as program: + print ("ops", program._instructions) + program.binfile.seek(0) + insns = load(program.binfile) + #for insn in insns: + #print ("insn", insn) + insns = list(insns) + print ("insns", insns) + for i, line in enumerate(dump(insns, verbose=False, short=True)): + print("instruction", repr(line), repr(expected[i])) + self.assertEqual(expected[i], line, + "instruction %i do not match " + "'%s' expected '%s'" % (i, line, expected[i])) + + def test_1_svshape2(self): + expected = [ + 'svshape2 12,1,15,5,0,0' + ] + isa = SVP64Asm(expected) + lst = list(isa) + with Program(lst, bigendian=False) as program: + print ("ops", program._instructions) + program.binfile.seek(0) + insns = load(program.binfile) + #for insn in insns: + #print ("insn", insn) + insns = list(insns) + print ("insns", insns) + for i, line in enumerate(dump(insns, verbose=False, short=True)): + print("instruction", repr(line), repr(expected[i])) + self.assertEqual(expected[i], line, + "instruction %i do not match " + "'%s' expected '%s'" % (i, line, expected[i])) + +if __name__ == "__main__": + unittest.main() + -- 2.30.2