From 8f54a70b7328721a7297dcd9321a42bd98bb38c9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 Jun 2020 15:40:36 +0100 Subject: [PATCH] move setup/check memory into helper functions for use in test_core.py --- src/soc/fu/compunits/test/test_compunit.py | 63 ++++++++++++---------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 554b6ded..7f14bb12 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -103,6 +103,38 @@ def get_inp_indexed(cu, inp): res[i] = inp[wrop] return res +def setup_test_memory(l0, sim): + mem = l0.mem.mem + print ("before, init mem", mem.depth, mem.width, mem) + for i in range(mem.depth): + data = sim.mem.ld(i*8, 8, False) + print ("init ", i, hex(data)) + yield mem._array[i].eq(data) + yield Settle() + for k, v in sim.mem.mem.items(): + print (" %6x %016x" % (k, v)) + print ("before, nmigen mem dump") + for i in range(mem.depth): + actual_mem = yield mem._array[i] + print (" %6i %016x" % (i, actual_mem)) + + +def check_sim_memory(dut, l0, sim, code): + mem = l0.mem.mem + print ("sim mem dump") + for k, v in sim.mem.mem.items(): + print (" %6x %016x" % (k, v)) + print ("nmigen mem dump") + for i in range(mem.depth): + actual_mem = yield mem._array[i] + print (" %6i %016x" % (i, actual_mem)) + + for i in range(mem.depth): + expected_mem = sim.mem.ld(i*8, 8, False) + actual_mem = yield mem._array[i] + dut.assertEqual(expected_mem, actual_mem, + "%s %d %x %x" % (code, i, + expected_mem, actual_mem)) class TestRunner(FHDLTestCase): def __init__(self, test_data, fukls, iodef, funit): @@ -152,20 +184,7 @@ class TestRunner(FHDLTestCase): # initialise memory if self.funit == Function.LDST: - mem = l0.mem.mem - print ("before, init mem", mem.depth, mem.width, mem) - for i in range(mem.depth): - data = sim.mem.ld(i*8, 8, False) - print ("init ", i, hex(data)) - yield mem._array[i].eq(data) - yield Settle() - for k, v in sim.mem.mem.items(): - print (" %6x %016x" % (k, v)) - print ("before, nmigen mem dump") - for i in range(mem.depth): - actual_mem = yield mem._array[i] - print (" %6i %016x" % (i, actual_mem)) - + yield from setup_test_memory(l0, sim) index = sim.pc.CIA.value//4 while index < len(instructions): @@ -244,21 +263,7 @@ class TestRunner(FHDLTestCase): # sigh. hard-coded. test memory if self.funit == Function.LDST: - mem = l0.mem.mem - print ("sim mem dump") - for k, v in sim.mem.mem.items(): - print (" %6x %016x" % (k, v)) - print ("nmigen mem dump") - for i in range(mem.depth): - actual_mem = yield mem._array[i] - print (" %6i %016x" % (i, actual_mem)) - - for i in range(mem.depth): - expected_mem = sim.mem.ld(i*8, 8, False) - actual_mem = yield mem._array[i] - self.assertEqual(expected_mem, actual_mem, - "%s %d %x %x" % (code, i, - expected_mem, actual_mem)) + yield from check_sim_memory(self, l0, sim, code) sim.add_sync_process(process) -- 2.30.2