From 8f567ee9f4a80cd68a07a1339d31f5e98136bd27 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 19 Apr 2022 13:09:00 +0100
Subject: [PATCH]

---
 openpower/isa/svfixedarith.mdwn | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index e51e292b2..1cb17ac42 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -32,15 +32,19 @@ Special Registers Altered:
 
 # Twin Multiply and Add  Doubleword
 
-<!-- SVP64: RC-as-source and RC-as-dest have separate EXTRA2 -->
-<!-- RT, RA have EXTRA2 marking. RB is always scalar (r0-31) -->
 * maddx RT,RA,RB,RC
 
+    <!-- SVP64: RC-as-source and RC-as-dest have separate EXTRA2 -->
+    <!-- RT, RA have EXTRA2 marking. RB is always scalar (r0-31) -->
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
     RC <- sum[0:63]
 
+Special Registers Altered:
+
+    None
+
 # Twin Multiply and Subtract Doubleword
 
 * msubx RT,RA,RB,RC
-- 
2.30.2