From 8f5d685581c011dd907c692b63b4e340a6de9b8d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 4 Nov 1998 19:30:29 -0800 Subject: [PATCH] alpha.md (addsi3, subsi3): Expand to a DImode temporary so as to expose this midpoint to CSE. * alpha.md (addsi3, subsi3): Expand to a DImode temporary so as to expose this midpoint to CSE. From-SVN: r23536 --- gcc/ChangeLog | 5 +++++ gcc/config/alpha/alpha.md | 18 ++++++++++-------- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 29399945fb2..f851757cb8b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Thu Nov 5 03:29:19 1998 Richard Henderson + + * alpha.md (addsi3, subsi3): Expand to a DImode temporary so as + to expose this midpoint to CSE. + Thu Nov 5 03:42:54 1998 David S. Miller * config/sparc/sparc.md (movdf_const_intreg_sp64): Enable again. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index bcd0b1e1fa8..c88497e3b35 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -426,10 +426,11 @@ (match_operand:SI 2 "add_operand" "")))] "" " -{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), - gen_rtx_PLUS (DImode, - gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2])))); +{ + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_adddi3 (tmp, gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2]))); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); DONE; } ") @@ -712,10 +713,11 @@ (match_operand:SI 2 "reg_or_8bit_operand" "")))] "" " -{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]), - gen_rtx_MINUS (DImode, - gen_lowpart (DImode, operands[1]), - gen_lowpart (DImode, operands[2])))); +{ + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_subdi3 (tmp, gen_lowpart (DImode, operands[1]), + gen_lowpart (DImode, operands[2]))); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp)); DONE; } ") -- 2.30.2