From 8f6a40bb418e346a78af5a83a5bc20f0ed538d57 Mon Sep 17 00:00:00 2001
From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sun, 10 Apr 2022 03:39:52 -0500
Subject: [PATCH] Don't reset the core / peripherals on DRAM controller reset
 request

---
 examples/ecp5_crg.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/ecp5_crg.py b/examples/ecp5_crg.py
index cda8a99..931168e 100644
--- a/examples/ecp5_crg.py
+++ b/examples/ecp5_crg.py
@@ -242,7 +242,7 @@ class ECP5CRG(Elaboratable):
         reset_ok = Signal(reset_less=True)
         m.d.comb += reset_ok.eq(~pll.locked|~pod_done)
         m.d.comb += ResetSignal("init").eq(reset_ok)
-        m.d.comb += ResetSignal("sync").eq(reset_ok|self.ddr_clk_reset)
+        m.d.comb += ResetSignal("sync").eq(reset_ok)
         m.d.comb += ResetSignal("dramsync").eq(reset_ok|self.ddr_clk_reset)
 
         # # Generating sync (100Mhz) from sync2x
-- 
2.30.2