From 8f745b47dabdbe80780e9c836b9caa7af2c11f75 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 24 Sep 2020 20:55:10 +0100 Subject: [PATCH] enable GPIO pads through C4M JTAG --- src/soc/litex/florent/libresoc/core.py | 28 ++++++++++++++++++++++---- src/soc/litex/florent/ls180soc.py | 19 +++++++++-------- 2 files changed, 33 insertions(+), 14 deletions(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index c366961a..21bded3f 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -34,6 +34,11 @@ def make_wb_slave(prefix, obj): res['o_%s__%s' % (prefix, o)] = getattr(obj, o) return res +def make_pad(res, dirn, name, suffix, cpup, iop): + cpud, iod = ('i', 'o') if dirn else ('o', 'i') + res['%s_%s__%s' % (cpud, name, suffix)] = cpup + res['%s_%s__%s' % (iod, name, suffix)] = iop + def make_jtag_ioconn(res, pin, cpupads, iopads): (fn, pin, iotype, pin_name) = pin @@ -45,17 +50,31 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): io = iopads[fn] sigs = [] + name = "%s_%s" % (fn, pin) + + if iotype in (IOType.In, IOType.Out): + cpup = getattr(cpu, pin) + iop = getattr(io, pin) + if iotype == IOType.Out: # output from the pad is routed through C4M JTAG and so # is an *INPUT* into core. ls180soc connects this to "real" peripheral - res['i_%s_%s_core__o' % (fn, pin)] = getattr(cpu, pin) - res['o_%s_%s_pad__o' % (fn, pin)] = getattr(io, pin) + make_pad(res, True, name, "o", cpup, iop) elif iotype == IOType.In: # input to the pad is routed through C4M JTAG and so # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral - res['o_%s_%s_core__i' % (fn, pin)] = getattr(cpu, pin) - res['i_%s_%s_pad__i' % (fn, pin)] = getattr(io, pin) + make_pad(res, False, name, "i", cpup, iop) + + elif iotype == IOType.InTriOut: + if fn == 'gpio': # sigh decode GPIO special-case + idx = int(pin[4:]) + cpup, iop = cpu.i[idx], io.i[idx] + make_pad(res, False, name, "i", cpup, iop) + cpup, iop = cpu.o[idx], io.o[idx] + make_pad(res, True, name, "o", cpup, iop) + cpup, iop = cpu.oe[idx], io.oe[idx] + make_pad(res, True, name, "oe", cpup, iop) if iotype in (IOType.In, IOType.InTriOut): sigs.append(("i", 1)) @@ -64,6 +83,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads): if iotype in (IOType.TriOut, IOType.InTriOut): sigs.append(("oe", 1)) + class LibreSoC(CPU): name = "libre_soc" human_name = "Libre-SoC" diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 0ddea034..21ecbb4c 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -382,16 +382,15 @@ class LibreSoCSim(SoCCore): self.irq.add("uart", use_loc_if_exists=True) # GPIOs (bi-directional) - if False: - gpio_core_pads = self.cpu.cpupads['gpio'] - self.submodules.gpio = GPIOTristateASIC(gpio_core_pads) - self.add_csr("gpio") - - gpio_pads = platform.request("gpio_litex") - gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads - self.comb += gpio_pads.i.eq(gpio_io_pads.i) - self.comb += gpio_io_pads.o.eq(gpio_pads.o) - self.comb += gpio_io_pads.oe.eq(gpio_pads.oe) + gpio_core_pads = self.cpu.cpupads['gpio'] + self.submodules.gpio = GPIOTristateASIC(gpio_core_pads) + self.add_csr("gpio") + + gpio_pads = platform.request("gpio_litex") + gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads + self.comb += gpio_pads.i.eq(gpio_io_pads.i) + self.comb += gpio_io_pads.o.eq(gpio_pads.o) + self.comb += gpio_io_pads.oe.eq(gpio_pads.oe) # SPI Master self.submodules.spi_master = SPIMaster( -- 2.30.2