From 8f8e7fe08edcc40f57edd5b3dd2a629394e624a2 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Thu, 15 Nov 2007 16:38:09 -0500
Subject: [PATCH] put the flattenIndex stuff back in O3 AND put fatal() back in
 faults

--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
---
 src/cpu/o3/thread_context_impl.hh | 38 ++++++++++++++++++++++++++++++-
 src/sim/faults.cc                 |  4 ++--
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 2d329b056..865d58635 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -289,9 +289,13 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
     // Copy the misc regs.
     TheISA::copyMiscRegs(tc, this);
 
-    // Then finally set the PC and the next PC.
+    // Then finally set the PC, the next PC, the nextNPC, the micropc, and the
+    // next micropc.
     cpu->setPC(tc->readPC(), tid);
     cpu->setNextPC(tc->readNextPC(), tid);
+    cpu->setNextNPC(tc->readNextNPC(), tid);
+    cpu->setMicroPC(tc->readMicroPC(), tid);
+    cpu->setNextMicroPC(tc->readNextMicroPC(), tid);
 #if !FULL_SYSTEM
     this->thread->funcExeInst = tc->readFuncExeInst();
 #endif
@@ -314,6 +318,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     switch(width) {
       case 32:
         return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
@@ -329,6 +334,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
 }
 
@@ -337,6 +343,7 @@ TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
 {
     DPRINTF(Fault, "Reading floatint register through the TC!\n");
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
 }
 
@@ -344,6 +351,7 @@ template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
 }
 
@@ -364,6 +372,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     switch(width) {
       case 32:
         cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
@@ -383,6 +392,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
 
     if (!thread->trapPending && !thread->inSyscall) {
@@ -396,6 +406,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
                                              int width)
 {
     DPRINTF(Fault, "Setting floatint register through the TC!\n");
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
@@ -408,6 +419,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
+    reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
@@ -440,6 +452,30 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
     }
 }
 
+template <class Impl>
+void
+O3ThreadContext<Impl>::setMicroPC(uint64_t val)
+{
+    cpu->setMicroPC(val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
+{
+    cpu->setNextMicroPC(val, thread->readTid());
+
+    // Squash if we're not already in a state update mode.
+    if (!thread->trapPending && !thread->inSyscall) {
+        cpu->squashFromTC(thread->readTid());
+    }
+}
+
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 6149a8335..0fe853785 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -40,7 +40,7 @@
 #if !FULL_SYSTEM
 void FaultBase::invoke(ThreadContext * tc)
 {
-    panic("fault (%s) detected @ PC %p", name(), tc->readPC());
+    fatal("fault (%s) detected @ PC %p", name(), tc->readPC());
 }
 #else
 void FaultBase::invoke(ThreadContext * tc)
@@ -54,7 +54,7 @@ void FaultBase::invoke(ThreadContext * tc)
 
 void UnimpFault::invoke(ThreadContext * tc)
 {
-    panic("Unimpfault: %s\n", panicStr.c_str());
+    fatal("Unimpfault: %s\n", panicStr.c_str());
 }
 
 #if !FULL_SYSTEM
-- 
2.30.2