From 8fba8d4ee7632ae185f70356093e10a563ea64cd Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 13 Aug 2013 11:34:01 -0700 Subject: [PATCH] i965: Add Gen6 depth stall flushes before disabling depth in BLORP. We emit these before configuring depth in the normal path, or actually using the depth buffer in BLORP - we just failed to emit them when disabling depth altogether. On Sandybridge, this also requires the post_sync_nonzero flush. Signed-off-by: Kenneth Graunke Reviewed-by: Chad Versace Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index a4a90817a8c..129c11361a6 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -914,6 +914,9 @@ static void gen6_blorp_emit_depth_disable(struct brw_context *brw, const brw_blorp_params *params) { + intel_emit_post_sync_nonzero_flush(brw); + intel_emit_depth_stall_flushes(brw); + BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | -- 2.30.2