From 8fc152e6e1710bfe32e2eea9dee0ec1f415ce719 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 11 Sep 2023 18:16:50 -0700 Subject: [PATCH] remove grev, leaving unit tests for later use by grevlut --- openpower/isa/bitmanip.mdwn | 80 ------------------- openpower/isatables/RM-1P-2S1D.csv | 2 - openpower/isatables/RM-2P-1S1D.csv | 2 - openpower/isatables/fields.text | 16 +--- openpower/isatables/minor_5.csv | 4 - src/openpower/decoder/formal/test_decoder2.py | 2 - src/openpower/decoder/isa/caller.py | 2 +- src/openpower/decoder/power_decoder2.py | 3 - src/openpower/decoder/power_enums.py | 8 +- src/openpower/test/bitmanip/bitmanip_cases.py | 8 +- 10 files changed, 12 insertions(+), 115 deletions(-) diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index 830962c9..3b0cc8e8 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -21,86 +21,6 @@ Special Registers Altered: CR0 (if Rc=1) -# Generalized Bit-Reverse - -X-Form - -* grev RT,RA,RB (Rc=0) -* grev. RT,RA,RB (Rc=1) - -Pseudo-code: - - result <- [0] * XLEN - b <- EXTZ64(RB) - do i = 0 to XLEN - 1 - idx <- b[64-log2(XLEN):63] ^ i - result[i] <- (RA)[idx] - RT <- result - -Special Registers Altered: - - CR0 (if Rc=1) - -# Generalized Bit-Reverse Immediate - -XB-Form - -* grevi RT,RA,XBI (Rc=0) -* grevi. RT,RA,XBI (Rc=1) - -Pseudo-code: - - result <- [0] * XLEN - do i = 0 to XLEN - 1 - idx <- XBI[6-log2(XLEN):5] ^ i - result[i] <- (RA)[idx] - RT <- result - -Special Registers Altered: - - CR0 (if Rc=1) - -# Generalized Bit-Reverse Word - -X-Form - -* grevw RT,RA,RB (Rc=0) -* grevw. RT,RA,RB (Rc=1) - -Pseudo-code: - - result <- [0] * (XLEN / 2) - a <- (RA)[XLEN/2:XLEN-1] - b <- EXTZ64(RB) - do i = 0 to XLEN / 2 - 1 - idx <- b[64-log2(XLEN/2):63] ^ i - result[i] <- a[idx] - RT <- ([0] * (XLEN / 2)) || result - -Special Registers Altered: - - CR0 (if Rc=1) - -# Generalized Bit-Reverse Word Immediate - -X-Form - -* grevwi RT,RA,SH (Rc=0) -* grevwi. RT,RA,SH (Rc=1) - -Pseudo-code: - - result <- [0] * (XLEN / 2) - a <- (RA)[XLEN/2:XLEN-1] - do i = 0 to XLEN / 2 - 1 - idx <- SH[5-log2(XLEN/2):4] ^ i - result[i] <- a[idx] - RT <- ([0] * (XLEN / 2)) || result - -Special Registers Altered: - - CR0 (if Rc=1) - # Add With Shift By Immediate Z23-Form diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index b70d617c..a9fc8956 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -98,8 +98,6 @@ divduo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 -grev,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 -grevw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 fdivs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fadds,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index b1e2ce66..e3e0fcab 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -164,5 +164,3 @@ sradi,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 sradi,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 extswsli,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 extswsli,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 -grevi,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 -grevwi,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 8e11b843..ecf5ab68 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -200,10 +200,6 @@ |0 |6 |11 |16 |21 |30|31 | | PO | RS | RA | sh | XO |sh|Rc | -# 1.6.15 XB-FORM - |0 |6 |11 |16 |22 |31 | - | PO | RT | RA | XBI | XO |Rc | - # 1.6.16 XO-FORM |0 |6 |11 |13 |16 |21 |22 |31 | | PO | RT | RA | RB | OE | XO | Rc | @@ -766,7 +762,7 @@ RA (11:15) Field used to specify a GPR to be used as a source or as a target. - Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, XB, TLI, Z23 + Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, MM, TX, VA, VA2, VX, X, XO, XS, SVL, TLI, Z23 RB (16:20) Field used to specify a GPR to be used as a source. @@ -788,7 +784,7 @@ 1 Set Condition Register Field 0 or Field 1 as described in Section 2.3.1, 'Condition Regis- ter' on page 30. - Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, XB, TLI, DCT + Formats: A, M, MD, MDS, MM, VA2, X, XFL, XO, XS, Z22, Z23, SVL, TLI, DCT RIC (12:13) Field used to specify what types of entries to inval- idate for tlbie[l]. @@ -817,7 +813,7 @@ Formats: DS, X RT (6:10) Field used to specify a GPR to be used as a target. - Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, XB, TLI, Z23 + Formats: A, BM2, D, DQE, DS, DX, MM, VA, VA2, VX, X, XFX, XO, XX2, SVL, TLI, Z23 RTp (6:10) Field used to specify an even/odd pair of GPRs to be concatenated and used as a target. @@ -1047,10 +1043,6 @@ XBI (21:24) Field used to specify a bit in the XER. Formats: MDS, MDS, TX - XBI (16:21) - Field used to specify a 6-bit unsigned immediate for bit manipulation - instructions, such as grevi. - Formats: XB XO (21:23,26:31) Extended opcode field. Formats: SVM2 @@ -1077,7 +1069,7 @@ Formats: VX XO (22:30) Extended opcode field. - Formats: XO, XX3, Z22, XB + Formats: XO, XX3, Z22 XO (22:31) Extended opcode field. Formats: VC diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index 87baf549..742d7b69 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,6 +1,2 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg --011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -0011110110-,SHIFT_ROT,OP_GREV,RA,CONST_SH32,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,grevwi,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/formal/test_decoder2.py b/src/openpower/decoder/formal/test_decoder2.py index 15e3538f..7f862eac 100644 --- a/src/openpower/decoder/formal/test_decoder2.py +++ b/src/openpower/decoder/formal/test_decoder2.py @@ -109,8 +109,6 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.imm_data.data == dec.sh) with m.Case(In2Sel.CONST_SH32): comb += Assert(pdecode2.e.imm_data.data == dec.SH32) - with m.Case(In2Sel.CONST_XBI): - comb += Assert(pdecode2.e.imm_data.data == dec.FormXB.XBI) with m.Default(): comb += Assert(0) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 4cdc6b8b..eaac32b5 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1959,7 +1959,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): "brh", "brw", "brd", 'setvl', 'svindex', 'svremap', 'svstep', 'svshape', 'svshape2', - 'grev', 'ternlogi', 'bmask', 'cprop', + 'ternlogi', 'bmask', 'cprop', 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd', 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du", "dsld", "dsrd", "maddedus", diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 83b813a6..b73fbe76 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -337,9 +337,6 @@ class DecodeBImm(Elaboratable): with m.Case(In2Sel.CONST_SH32): # unsigned - for shift comb += self.imm_out.data.eq(self.dec.SH32) comb += self.imm_out.ok.eq(1) - with m.Case(In2Sel.CONST_XBI): # unsigned - for grevi - comb += self.imm_out.data.eq(self.dec.FormXB.XBI) - comb += self.imm_out.ok.eq(1) return m diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index db7d1897..54e325ae 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -167,7 +167,7 @@ class Form(Enum): SVM2 = 33 # Simple-V SHAPE2 mode - fits into SVM SVRM = 34 # Simple-V REMAP mode TLI = 35 # ternlogi - XB = 36 + # 36 available BM2 = 37 # bmask SVI = 38 # Simple-V Index Mode VA2 = 39 @@ -771,8 +771,6 @@ _insns = [ "mffpr", "mffprs", "ctfpr", "ctfprs", "mtfpr", "mtfprs", - 'grev', 'grev.', 'grevi', 'grevi.', - 'grevw', 'grevw.', 'grevwi', 'grevwi.', "hrfid", "icbi", "icbt", "isel", "isync", "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx", # load byte "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double @@ -940,7 +938,7 @@ class MicrOp(Enum): OP_CBCDTD = 85 OP_TERNLOG = 86 OP_FETCH_FAILED = 87 - OP_GREV = 88 + # 88 available OP_MINMAX = 89 OP_AVGADD = 90 OP_ABSDIFF = 91 @@ -1026,7 +1024,7 @@ class In2Sel(Enum): FRBp = FRB CONST_SVD = 15 # for SVD-Form CONST_SVDS = 16 # for SVDS-Form - CONST_XBI = 17 + # 17 available CONST_DXHI4 = 18 # for addpcis CONST_DQ = 19 # for ld/st-quad diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py index 46550454..494ff0f0 100644 --- a/src/openpower/test/bitmanip/bitmanip_cases.py +++ b/src/openpower/test/bitmanip/bitmanip_cases.py @@ -98,7 +98,7 @@ class BitManipTestCase(TestAccumulatorBase): rb = hash_256(f"ternlogi rb {i}") % 2 ** 64 self.do_case_ternlogi(rc, rt, ra, rb, imm) - @skip_case("invalid, replaced by grevlut") + @skip_case("grev removed -- leaving code for later use in grevlut") def case_grev_random(self): for i in range(100): w = hash_256(f"grev w {i}") & 1 @@ -107,16 +107,16 @@ class BitManipTestCase(TestAccumulatorBase): rb = hash_256(f"grev rb {i}") % 2 ** 64 self.do_case_grev(w, is_imm, ra, rb) - @skip_case("invalid, replaced by grevlut") + @skip_case("grev removed -- leaving code for later use in grevlut") def case_grevi_1(self): self.do_case_grev(False, True, 14361919363078703450, 8396479064514513069) - @skip_case("invalid, replaced by grevlut") + @skip_case("grev removed -- leaving code for later use in grevlut") def case_grevi_2(self): self.do_case_grev(True, True, 397097147229333315, 8326716970539357702) - @skip_case("invalid, replaced by grevlut") + @skip_case("grev removed -- leaving code for later use in grevlut") def case_grevi_3(self): self.do_case_grev(True, True, 0xFFFF_FFFF_0000_0000, 6) -- 2.30.2