From 8fc6050bf747fb5d367b406013b9d6652b772344 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 19:05:49 +0000
Subject: [PATCH] add MSR to ldst operand debug gtkw

---
 src/openpower/test/runner.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index dd59e9fa..c429ee14 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -381,6 +381,7 @@ class TestRunnerBase(FHDLTestCase):
 
         traces += [('ld/st port interface', {'submodule': pi_module}, [
             'oper_r__insn_type',
+            'oper_r__msr',
             'ldst_port0_is_ld_i',
             'ldst_port0_is_st_i',
             'ldst_port0_busy_o',
-- 
2.30.2