From 8fd83a546b82e2ab3f7db5d470f3f3f1adcf972a Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Tue, 23 Sep 2014 07:17:19 +0000 Subject: [PATCH] AVX-512. Add masked vunpck[lh]pd. gcc/ * config/i386/sse.md (define_insn "avx_unpckhpd256"): Add masking. (define_insn "avx512vl_unpckhpd128_mask"): New. (define_expand "avx_movddup256"): Add masking. (define_expand "avx_unpcklpd256"): Ditto. (define_insn "*avx_unpcklpd256"): Ditto. (define_insn "avx512vl_unpcklpd128_mask"): New. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215493 --- gcc/ChangeLog | 17 +++++++++++ gcc/config/i386/sse.md | 66 +++++++++++++++++++++++++++++++----------- 2 files changed, 66 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f91e231f2e6..05928482775 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2014-09-23 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_insn "avx_unpckhpd256"): Add masking. + (define_insn "avx512vl_unpckhpd128_mask"): New. + (define_expand "avx_movddup256"): Add masking. + (define_expand "avx_unpcklpd256"): Ditto. + (define_insn "*avx_unpcklpd256"): Ditto. + (define_insn "avx512vl_unpcklpd128_mask"): New. + 2014-09-22 Joseph Myers * doc/tm.texi.in (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Remove. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 533308b2f50..ab2d3b18409 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7081,16 +7081,16 @@ (set_attr "mode" "V8DF")]) ;; Recall that the 256-bit unpck insns only shuffle within their lanes. -(define_insn "avx_unpckhpd256" - [(set (match_operand:V4DF 0 "register_operand" "=x") +(define_insn "avx_unpckhpd256" + [(set (match_operand:V4DF 0 "register_operand" "=v") (vec_select:V4DF (vec_concat:V8DF - (match_operand:V4DF 1 "register_operand" "x") - (match_operand:V4DF 2 "nonimmediate_operand" "xm")) + (match_operand:V4DF 1 "register_operand" "v") + (match_operand:V4DF 2 "nonimmediate_operand" "vm")) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)])))] - "TARGET_AVX" - "vunpckhpd\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX && " + "vunpckhpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "V4DF")]) @@ -7124,6 +7124,22 @@ }) +(define_insn "avx512vl_unpckhpd128_mask" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (vec_merge:V2DF + (vec_select:V2DF + (vec_concat:V4DF + (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "nonimmediate_operand" "vm")) + (parallel [(const_int 1) (const_int 3)])) + (match_operand:V2DF 3 "vector_move_operand" "0C") + (match_operand:QI 4 "register_operand" "Yk")))] + "TARGET_AVX512VL" + "vunpckhpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "V2DF")]) + (define_expand "vec_interleave_highv2df" [(set (match_operand:V2DF 0 "register_operand") (vec_select:V2DF @@ -7204,7 +7220,7 @@ (set_attr "mode" "V8DF")]) ;; Recall that the 256-bit unpck insns only shuffle within their lanes. -(define_expand "avx_movddup256" +(define_expand "avx_movddup256" [(set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF @@ -7212,9 +7228,9 @@ (match_dup 1)) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] - "TARGET_AVX") + "TARGET_AVX && ") -(define_expand "avx_unpcklpd256" +(define_expand "avx_unpcklpd256" [(set (match_operand:V4DF 0 "register_operand") (vec_select:V4DF (vec_concat:V8DF @@ -7222,20 +7238,20 @@ (match_operand:V4DF 2 "nonimmediate_operand")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] - "TARGET_AVX") + "TARGET_AVX && ") -(define_insn "*avx_unpcklpd256" - [(set (match_operand:V4DF 0 "register_operand" "=x,x") +(define_insn "*avx_unpcklpd256" + [(set (match_operand:V4DF 0 "register_operand" "=v,v") (vec_select:V4DF (vec_concat:V8DF - (match_operand:V4DF 1 "nonimmediate_operand" " x,m") - (match_operand:V4DF 2 "nonimmediate_operand" "xm,1")) + (match_operand:V4DF 1 "nonimmediate_operand" " v,m") + (match_operand:V4DF 2 "nonimmediate_operand" "vm,1")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] - "TARGET_AVX" + "TARGET_AVX && " "@ - vunpcklpd\t{%2, %1, %0|%0, %1, %2} - vmovddup\t{%1, %0|%0, %1}" + vunpcklpd\t{%2, %1, %0|%0, %1, %2} + vmovddup\t{%1, %0|%0, %1}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "V4DF")]) @@ -7268,6 +7284,22 @@ operands[4] = gen_reg_rtx (V4DFmode); }) +(define_insn "avx512vl_unpcklpd128_mask" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (vec_merge:V2DF + (vec_select:V2DF + (vec_concat:V4DF + (match_operand:V2DF 1 "register_operand" "v") + (match_operand:V2DF 2 "nonimmediate_operand" "vm")) + (parallel [(const_int 0) (const_int 2)])) + (match_operand:V2DF 3 "vector_move_operand" "0C") + (match_operand:QI 4 "register_operand" "Yk")))] + "TARGET_AVX512VL" + "vunpcklpd\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "V2DF")]) + (define_expand "vec_interleave_lowv2df" [(set (match_operand:V2DF 0 "register_operand") (vec_select:V2DF -- 2.30.2