From 8fe60dbf6d5d1040b4ec70f84babd8b1ddf8df2f Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 9 Jul 2020 16:26:16 +0200
Subject: [PATCH] Make power-on delay signal synchronous

---
 examples/crg.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/crg.py b/examples/crg.py
index 092c319..117503e 100644
--- a/examples/crg.py
+++ b/examples/crg.py
@@ -109,7 +109,7 @@ class ECPIX5CRG(Elaboratable):
         pod_done = Signal()
         with m.If(podcnt != 0):
             m.d.rawclk += podcnt.eq(podcnt-1)
-        m.d.comb += pod_done.eq(podcnt == 0)
+        m.d.rawclk += pod_done.eq(podcnt == 0)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from clk100
         cd_sync2x = ClockDomain("sync2x", local=False)
-- 
2.30.2