From 8fea3ef935918b2dd528c98474f6fb3b12111fb2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 24 Sep 2022 17:31:00 +0100 Subject: [PATCH] add extra RC1 test, without VLI. --- .../isa/test_caller_svp64_dd_ffirst.py | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py index f03cb7f7..7d728a86 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py @@ -66,6 +66,47 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) + def test_sv_addi_ffirst_rc1(self): + lst = SVP64Asm([ "sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1) + ]) + lst = list(lst) + + # SVSTATE + svstate = SVP64State() + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + gprs = [0] * 64 + gprs[8] = 3 + vec = [9, 8, 3, 4] + + res = [] + # store GPRs + for i, x in enumerate(vec): + gprs[i] = x + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs=gprs, + svstate=svstate) + for i in range(4): + val = sim.gpr(i).value + res.append(val) + print ("i", i, val) + # confirm that the results are as expected + expected = deepcopy(vec) + for i in range(4): + expected[i] -= gprs[8] + if expected[i] == 0: + break + for i, v in enumerate(res): + self.assertEqual(v, expected[i]) + + self.assertEqual(sim.svstate.vl, 2) + self.assertEqual(sim.svstate.maxvl, 4) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) + def test_sv_addi_ffirst_vli(self): lst = SVP64Asm([ "sv.subf/ff=RC1/vli *0,8,*0" ]) -- 2.30.2