From 901541c2ec9d5b6a9321ab2bb2ef9d7c63a9e09d Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 29 Apr 2016 11:17:58 -0700 Subject: [PATCH] Continue works well enough for DebugTest.test_exit --- riscv/gdbserver.cc | 10 ++++++++++ riscv/processor.cc | 1 - 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 629dc27..189a1ea 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -72,6 +72,12 @@ static uint32_t csrsi(unsigned int csr, uint8_t imm) { MATCH_CSRRSI; } +static uint32_t csrci(unsigned int csr, uint8_t imm) { + return (csr << 20) | + (bits(imm, 4, 0) << 15) | + MATCH_CSRRCI; +} + static uint32_t csrr(unsigned int rd, unsigned int csr) { return (csr << 20) | (rd << 7) | MATCH_CSRRS; } @@ -696,6 +702,10 @@ void gdbserver_t::handle_continue(const std::vector &packet) return send_packet("E30"); } + write_debug_ram(0, csrci(DCSR_ADDRESS, DCSR_HALT_MASK)); + write_debug_ram(1, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 1*5)))); + set_interrupt(0); + // TODO p->set_halted(false, HR_NONE); // TODO running = true; } diff --git a/riscv/processor.cc b/riscv/processor.cc index ad84b6e..d937f2e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -487,7 +487,6 @@ reg_t processor_t::get_csr(int which) (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) | (state.dcsr.halt << DCSR_HALT_OFFSET) | (state.dcsr.cause << DCSR_CAUSE_OFFSET); - fprintf(stderr, "DCSR: 0x%x\n", value); return value; } case DPC_ADDRESS: -- 2.30.2