From 902d2faadf37a5627ab2cbcd8993825c8749ec82 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 11 Jul 2002 15:33:02 +0000 Subject: [PATCH] applied Eric Anholt's patch for Athlon SSE --- src/mesa/x86/common_x86.c | 16 ++++++++++++++-- src/mesa/x86/common_x86_asm.S | 15 ++++++++++++++- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/mesa/x86/common_x86.c b/src/mesa/x86/common_x86.c index bcffb6a01be..aaef4f8349e 100644 --- a/src/mesa/x86/common_x86.c +++ b/src/mesa/x86/common_x86.c @@ -1,4 +1,4 @@ -/* $Id: common_x86.c,v 1.18 2002/06/29 19:48:17 brianp Exp $ */ +/* $Id: common_x86.c,v 1.19 2002/07/11 15:33:02 brianp Exp $ */ /* * Mesa 3-D graphics library @@ -38,6 +38,10 @@ #if defined(USE_SSE_ASM) && defined(__linux__) #include #endif +#if defined(USE_SSE_ASM) && defined(__FreeBSD__) +#include +#include +#endif #include "context.h" #include "common_x86_asm.h" @@ -213,8 +217,16 @@ static void check_os_sse_support( void ) message( "Cannot test OS support for SSE, disabling to be safe.\n" ); _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ +#elif defined(__FreeBSD__) + { + int ret, len, enabled; + len = sizeof(enabled); + ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0); + if (ret || !enabled) + _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); + } #else - /* Do nothing on non-Linux platforms for now. + /* Do nothing on other platforms for now. */ message( "Not testing OS support for SSE, leaving enabled.\n" ); #endif /* __linux__ */ diff --git a/src/mesa/x86/common_x86_asm.S b/src/mesa/x86/common_x86_asm.S index f877fd57c28..6fe7443c814 100644 --- a/src/mesa/x86/common_x86_asm.S +++ b/src/mesa/x86/common_x86_asm.S @@ -1,4 +1,4 @@ -/* $Id: common_x86_asm.S,v 1.10 2002/06/11 01:26:58 brianp Exp $ */ +/* $Id: common_x86_asm.S,v 1.11 2002/07/11 15:33:02 brianp Exp $ */ /* * Mesa 3-D graphics library @@ -129,6 +129,15 @@ LLBL(cpuid_amd): * information after we verify that the extended functions are * supported. */ + /* The features we need are almost all in the extended set. The + * exception is SSE enable, which is in the standard set (0x1). + */ + MOV_L ( CONST(0x1), EAX ) + CPUID + TEST_L ( EAX, EAX ) + JZ ( LLBL (cpuid_failed) ) + MOV_L ( EDX, ESI ) + MOV_L ( CONST(0x80000000), EAX ) CPUID TEST_L ( EAX, EAX ) @@ -137,6 +146,10 @@ LLBL(cpuid_amd): MOV_L ( CONST(0x80000001), EAX ) CPUID MOV_L ( EDX, EAX ) + + AND_L ( CONST(0x02000000), ESI ) /* OR in the SSE bit */ + OR_L ( ESI, EAX ) + JMP ( LLBL (cpuid_done) ) LLBL(cpuid_other): -- 2.30.2