From 9047d0fbde58a11ebe7c38d440eba0f921d96b88 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 11 May 2020 11:30:34 -0400 Subject: [PATCH] Check output of cr0 from alu --- src/soc/alu/output_stage.py | 2 +- src/soc/alu/test/test_pipe_caller.py | 15 +++++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py index 14953ca3..f5a50160 100644 --- a/src/soc/alu/output_stage.py +++ b/src/soc/alu/output_stage.py @@ -41,7 +41,7 @@ class ALUOutputStage(PipeModBase): comb += so.eq(self.i.so | self.i.ov) comb += self.o.o.eq(o) - comb += self.o.cr0.eq(Cat(is_negative, is_positive, is_zero, so)) + comb += self.o.cr0.eq(Cat(so, is_zero, is_positive, is_negative)) comb += self.o.so.eq(so) comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index c2520dde..6e6a69b2 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -59,7 +59,6 @@ def set_extra_alu_inputs(alu, dec2, sim): yield alu.p.data_i.so.eq(so) - class ALUTestCase(FHDLTestCase): def run_tst(self, program, initial_regs, initial_sprs): m = Module() @@ -117,12 +116,20 @@ class ALUTestCase(FHDLTestCase): expected = simulator.gpr(write_reg_idx).value print(f"expected {expected:x}, actual: {alu_out:x}") self.assertEqual(expected, alu_out) + yield from self.check_extra_alu_outputs(alu, pdecode2, + simulator) sim.add_sync_process(process) with sim.write_vcd("simulator.vcd", "simulator.gtkw", traces=[]): sim.run() return simulator + def check_extra_alu_outputs(self, alu, dec2, sim): + rc = yield dec2.e.rc.data + if rc: + cr_expected = sim.crl[0].get_range().value + cr_actual = yield alu.n.data_o.cr0 + self.assertEqual(cr_expected, cr_actual) def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): simulator = self.run_tst(prog, initial_regs, initial_sprs) @@ -214,10 +221,10 @@ class ALUTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs) def test_adde(self): - lst = ["adde 3, 1, 2"] + lst = ["adde. 5, 6, 7"] initial_regs = [0] * 32 - initial_regs[1] = 0xbeef - initial_regs[2] = 0xdead + initial_regs[6] = random.randint(0, (1<<64)-1) + initial_regs[7] = random.randint(0, (1<<64)-1) initial_sprs = {} xer = SelectableInt(0, 64) xer[XER_bits['CA']] = 1 -- 2.30.2