From 9053d0803a58535d8098f083033f81f96bf99562 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Nov 2019 08:56:52 +0100 Subject: [PATCH] soc_sdram: remove use_full_memory_we parameter (always used as True) --- litex/soc/integration/soc_sdram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 0dc8ff9b..a8ac01ed 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -42,7 +42,7 @@ class SoCSDRAM(SoCCore): raise FinalizeError self._wb_sdram_ifs.append(interface) - def register_sdram(self, phy, geom_settings, timing_settings, use_full_memory_we=True, **kwargs): + def register_sdram(self, phy, geom_settings, timing_settings, **kwargs): assert not self._sdram_phy self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning @@ -99,7 +99,7 @@ class SoCSDRAM(SoCCore): # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx... from litex.build.xilinx.vivado import XilinxVivadoToolchain - if isinstance(self.platform.toolchain, XilinxVivadoToolchain) and use_full_memory_we: + if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) else: -- 2.30.2