From 90683493b30100d86536a68011e02a1714cecf97 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Jun 2022 19:08:34 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index aed1adabc..7284a2147 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -32,11 +32,12 @@ Other "modifications" such as saturation or Data-dependent Fail-First likewise are post-augmentation or post-analysis, and do not actually fundamentally change an add operation into a subtract for example. -*(An experiment was attempted to modify LD-immediate instructions +*(In an early Draft of SVP64, +an experiment was attempted, to modify LD-immediate instructions to include a third RC register i.e. reinterpret the normal -v3.0 32-bit instruction as a -different encoding if SVP64-prefixed: it did not go well. +v3.0 32-bit instruction as a completely +different encoding if SVP64-prefixed. It did not go well. The complexity that resulted in the decode phase was too great. The lesson was learned, the hard way: it is infinitely preferable to add a 32-bit Scalar Load-with-Shift -- 2.30.2