From 907570fdb16fa0baf737a79017b28ce4b980a926 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Sep 2021 00:05:07 +0100 Subject: [PATCH] add first "ExpectedState" to HDL-sim ALU test cases --- src/openpower/test/alu/alu_cases.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py index a4b32577..13efdd53 100644 --- a/src/openpower/test/alu/alu_cases.py +++ b/src/openpower/test/alu/alu_cases.py @@ -5,6 +5,7 @@ from openpower.simulator.program import Program from openpower.decoder.selectable_int import SelectableInt from openpower.decoder.power_enums import XER_bits from openpower.decoder.isa.caller import special_sprs +from openpower.test.state import ExpectedState import unittest @@ -109,7 +110,9 @@ class ALUTestCase(TestAccumulatorBase): print(lst) initial_regs = [0] * 32 initial_regs[0] = 5 - self.add_case(Program(lst, bigendian), initial_regs) + e = ExpectedState(initial_regs, pc=4) + e.intregs[3] = 0x10000 + self.add_case(Program(lst, bigendian), initial_regs, expected=e) def case_addis_nonzero_r0(self): for i in range(10): -- 2.30.2