From 9097889338880eef69173edcac35d40b1d0940e5 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Fri, 2 Apr 2021 16:32:33 -0300 Subject: [PATCH] Disallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred --- src/soc/sv/trans/svp64.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index da4311b7..37d5abee 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -483,6 +483,15 @@ class SVP64Asm: elif encmode == 'svm': # sub-vector mode mapreduce_svm = True + if ptype == '2P': + # since m=xx takes precedence (overrides) sm=xx and dm=xx, + # treat them as mutually exclusive + if mask_m_specified: + assert not has_smask,\ + "cannot have both source-mask and predicate mask" + assert not has_pmask,\ + "cannot have both dest-mask and predicate mask" + # sanity-check that 2Pred mask is same mode if (has_pmask and has_smask) or mask_m_specified: assert smmode == pmmode, \ @@ -638,7 +647,7 @@ if __name__ == '__main__': 'sv.setb/vec2 5, 31', 'sv.setb/sw=8/ew=16 5, 31', 'sv.extsw./ff=eq 5, 31', - 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31', + 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31', 'sv.extsw./pr=eq 5.v, 31', 'sv.add. 5.v, 2.v, 1.v', 'sv.add./m=r3 5.v, 2.v, 1.v', -- 2.30.2