From 90a00ff010d9c0c800aeb28f763bd11b85702e42 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Thu, 7 Jun 2018 11:43:04 +0530
Subject: [PATCH] arch-power: Add fixed-point arithmetic add instructions

This adds the following arithmetic instructions:
  * Add PC Immediate Shifted (addpcis)

Change-Id: Id9de59427cbf8578fd75cbb7c98fb767d885d89a
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
 src/arch/power/insts/integer.cc        | 51 ++++++++++++++++++++++++++
 src/arch/power/insts/integer.hh        | 21 +++++++++++
 src/arch/power/isa/decoder.isa         |  6 +++
 src/arch/power/isa/formats/integer.isa | 11 ++++++
 4 files changed, 89 insertions(+)

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 62a8b26fb..293efdf56 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -215,6 +215,57 @@ IntImmArithOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 }
 
 
+string
+IntDispArithOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    bool printSrcs = true;
+    bool printDisp = true;
+    bool negateDisp = false;
+
+    // Generate the correct mnemonic
+    string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("addpcis")) {
+        printSrcs = false;
+        if (disp == 0) {
+            myMnemonic = "lnia";
+            printDisp = false;
+        } else if (disp < 0) {
+            myMnemonic = "subpcis";
+            negateDisp = true;
+        }
+    }
+
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, _destRegIdx[0]);
+    }
+
+    // Print the source register
+    if (_numSrcRegs > 0 && printSrcs) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, _srcRegIdx[0]);
+    }
+
+    // Print the displacement
+    if (printDisp) {
+        if (negateDisp) {
+            ss << ", " << -disp;
+        } else {
+            ss << ", " << disp;
+        }
+    }
+
+    return ss.str();
+}
+
+
 string
 IntShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 0c1513219..4ffd4691f 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -182,6 +182,27 @@ class IntImmArithOp : public IntArithOp
 };
 
 
+/**
+ * Class for integer arithmetic operations with displacement.
+ */
+class IntDispArithOp : public IntArithOp
+{
+  protected:
+
+    int32_t disp;
+
+    /// Constructor
+    IntDispArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntArithOp(mnem, _machInst, __opClass),
+        disp((int16_t)((machInst.d0 << 6) | (machInst.d1 << 1) | machInst.d2))
+    {
+    }
+
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
+};
+
+
 /**
  * Class for integer operations with a shift.
  */
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 210f2aea1..cc90f8537 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -137,6 +137,12 @@ decode PO default Unknown::unknown() {
         format MiscOp {
             150: isync({{ }}, [ IsSerializeAfter ]);
         }
+
+        default: decode DX_XO {
+            format IntDispArithOp {
+                2: addpcis({{ Rt = NIA + (disp << 16); }});
+            }
+        }
     }
 
     17: IntOp::sc({{ xc->syscall(R0, &fault); }},
diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index 9bbd65e70..54c35ebca 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -212,6 +212,17 @@ def format IntImmLogicOp(code, computeCR0 = 0, inst_flags = []) {{
 }};
 
 
+// Integer instructions with displacement that perform arithmetic.
+// There are no control flags to set.
+def format IntDispArithOp(code, inst_flags = []) {{
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
 // Integer instructions that perform logic operations. The result is
 // always written into Ra. All instructions have 2 versions depending on
 // whether the Rc bit is set to compute the CR0 code. This is determined
-- 
2.30.2