From 90a9100f6bf1af796d46b6ff73d1285d5daf16ba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 26 Apr 2021 10:32:42 +0100 Subject: [PATCH] comment read ack in sram --- src/soc/bus/sram.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/bus/sram.py b/src/soc/bus/sram.py index 1575e6ae..7d634909 100644 --- a/src/soc/bus/sram.py +++ b/src/soc/bus/sram.py @@ -71,7 +71,9 @@ class SRAM(Elaboratable): if self.memory.width > len(self.bus.dat_r): raise NotImplementedError - # read + # read - this relies on the read port producing data + # with one clock delay. the "ack" goes out on a sync + # which matches that m.submodules.rdport = rdport = self.memory.read_port() m.d.comb += [ rdport.addr.eq(self.bus.adr[:len(rdport.addr)]), -- 2.30.2