From 90bfeb22444df6ce779251522e47bf169e130f8e Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Mon, 1 Sep 2014 13:42:51 -0700 Subject: [PATCH] i965/vec4: Don't use instruction list after calculating the cfg. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +- src/mesa/drivers/dri/i965/brw_vec4.cpp | 14 +++++++------- .../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 3 ++- .../drivers/dri/i965/brw_vec4_live_variables.cpp | 2 +- .../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 8 ++++---- 5 files changed, 15 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 0a33063e966..d8c8643e91b 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -854,7 +854,7 @@ backend_visitor::dump_instructions(const char *name) } int ip = 0; - foreach_in_list(backend_instruction, inst, &instructions) { + foreach_block_and_inst(block, backend_instruction, inst, cfg) { if (!name) fprintf(stderr, "%d: ", ip++); dump_instruction(inst, file); diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index eae6d6f4862..ed1200db18e 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -332,7 +332,7 @@ vec4_visitor::opt_reduce_swizzle() { bool progress = false; - foreach_in_list_safe(vec4_instruction, inst, &instructions) { + foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG) continue; @@ -579,7 +579,7 @@ vec4_visitor::split_uniform_registers() * vector. The goal is to make elimination of unused uniform * components easier later. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -612,7 +612,7 @@ vec4_visitor::pack_uniform_registers() * expect unused vector elements when we've moved array access out * to pull constants, and from some GLSL code generators like wine. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -665,7 +665,7 @@ vec4_visitor::pack_uniform_registers() this->uniforms = new_uniform_count; /* Now, update the instructions for our repacked uniforms. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { int src = inst->src[i].reg; @@ -1223,7 +1223,7 @@ vec4_visitor::split_virtual_grfs() /* Check that the instructions are compatible with the registers we're trying * to split. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* If there's a SEND message loading from a GRF on gen7+, it needs to be * contiguous. */ @@ -1252,7 +1252,7 @@ vec4_visitor::split_virtual_grfs() this->virtual_grf_sizes[i] = 1; } - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF && split_grf[inst->dst.reg] && inst->dst.reg_offset != 0) { inst->dst.reg = (new_virtual_grf[inst->dst.reg] + @@ -1477,7 +1477,7 @@ void vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, bool interleaved) { - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* We have to support ATTR as a destination for GL_FIXED fixup. */ if (inst->dst.file == ATTR) { int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp index fe47b0f6e0b..65564c998e3 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp @@ -30,6 +30,7 @@ */ #include "brw_vec4.h" +#include "brw_cfg.h" extern "C" { #include "main/macros.h" } @@ -336,7 +337,7 @@ vec4_visitor::opt_copy_propagation() memset(&entries, 0, sizeof(entries)); - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* This pass only works on basic blocks. If there's flow * control, throw out all our information and start from * scratch. diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp index 5b7acf4de65..80b912a343b 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp @@ -214,7 +214,7 @@ vec4_visitor::calculate_live_intervals() * flow. */ int ip = 0; - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { int reg = inst->src[i].reg; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index b7426d29498..828a70e2752 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -57,7 +57,7 @@ vec4_visitor::reg_allocate_trivial() virtual_grf_used[i] = false; } - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF) virtual_grf_used[inst->dst.reg] = true; @@ -77,7 +77,7 @@ vec4_visitor::reg_allocate_trivial() } prog_data->total_grf = next; - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { assign(hw_reg_mapping, &inst->dst); assign(hw_reg_mapping, &inst->src[0]); assign(hw_reg_mapping, &inst->src[1]); @@ -238,7 +238,7 @@ vec4_visitor::reg_allocate() hw_reg_mapping[i] + virtual_grf_sizes[i]); } - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { assign(hw_reg_mapping, &inst->dst); assign(hw_reg_mapping, &inst->src[0]); assign(hw_reg_mapping, &inst->src[1]); @@ -264,7 +264,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) * spill/unspill we'll have to do, and guess that the insides of * loops run 10 times. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { spill_costs[inst->src[i].reg] += loop_scale; -- 2.30.2