From 90c168668c246a72a860408a2ebd4d98b7d96fa7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 27 Aug 2021 18:37:56 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index f0f16fbfd..89a32e7b0 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -210,7 +210,7 @@ The Mode table for operations except LD/ST and Branch Conditional | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 | | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | -| 01 | inv | dz RC1 | Rc=0: ffirst z/nonz | +| 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz | | 10 | N | dz sz | sat mode: N=0/1 u/s | | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz | @@ -224,7 +224,10 @@ than the normal 0..VL-1 * **CRM** affects the CR on reduce mode when Rc=1 * **SVM** sets "subvector" reduce mode * **N** sets signed/unsigned saturation. -**RC1** as if Rc=1, stores CRs *but not the result* +* **RC1** as if Rc=1, stores CRs *but not the result* +* **VLi** VL inclusive: in fail-first mode, the truncation of + VL *includes* the current element at the failure point rather + than excludes it from the count. For LD/ST Modes, see [[sv/ldst]]. For Branch modes, see [[sv/branches]] Immediate and Indexed LD/ST are both different, in order to support a large range of features -- 2.30.2