From 90c485fcc88751c8b123c9ae1f57319d9939f387 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 8 May 2020 13:15:44 +0200 Subject: [PATCH] integration/soc: add clock_domain parameter to add_etherbone. To allow using a sys_clk < 125MHz with a 1Gbps link. --- litex/soc/integration/soc.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index d45b32fd..012c486d 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1138,7 +1138,7 @@ class LiteXSoC(SoC): eth_tx_clk) # Add Etherbone -------------------------------------------------------------------------------- - def add_etherbone(self, name="etherbone", phy=None, + def add_etherbone(self, name="etherbone", phy=None, clock_domain=None, mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", udp_port = 1234): @@ -1151,9 +1151,21 @@ class LiteXSoC(SoC): mac_address = mac_address, ip_address = ip_address, clk_freq = self.clk_freq) + if clock_domain is not None: # FIXME: Could probably be avoided. + ethcore = ClockDomainsRenamer("eth_tx")(ethcore) self.submodules += ethcore + + # Clock domain renaming + if clock_domain is not None: # FIXME: Could probably be avoided. + self.clock_domains.cd_etherbone = ClockDomain("etherbone") + self.comb += self.cd_etherbone.clk.eq(ClockSignal(clock_domain)) + self.comb += self.cd_etherbone.rst.eq(ResetSignal(clock_domain)) + clock_domain = "etherbone" + else: + clock_domain = "sys" + # Etherbone - etherbone = LiteEthEtherbone(ethcore.udp, udp_port) + etherbone = LiteEthEtherbone(ethcore.udp, udp_port, cd=clock_domain) setattr(self.submodules, name, etherbone) self.add_wb_master(etherbone.wishbone.bus) # Timing constraints -- 2.30.2