From 9116d5861599cc99a608d53d3d0228f9944ce6af Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 28 Sep 2019 11:17:51 +0100 Subject: [PATCH] add standards tag --- nlnet_proposals.mdwn | 2 +- resources.mdwn | 7 +++++++ simple_v_extension/abridged_spec.mdwn | 2 ++ simple_v_extension/appendix.mdwn | 2 ++ simple_v_extension/specification.mdwn | 2 ++ simple_v_extension/specification/bitmanip.mdwn | 2 ++ simple_v_extension/specification/mv.x.rst | 2 ++ simple_v_extension/specification/sv.setvl.mdwn | 2 ++ simple_v_extension/sv_prefix_proposal.rst | 2 ++ simple_v_extension/vblock_format.mdwn | 2 ++ simple_v_extension/vector_ops.mdwn | 2 ++ zfpacc_proposal.mdwn | 2 ++ ztrans_proposal.mdwn | 2 ++ 13 files changed, 30 insertions(+), 1 deletion(-) diff --git a/nlnet_proposals.mdwn b/nlnet_proposals.mdwn index cf584ace3..384b35dec 100644 --- a/nlnet_proposals.mdwn +++ b/nlnet_proposals.mdwn @@ -9,7 +9,7 @@ added RADV, re-submitted 2019sep26 * [[nlnet_2019_gcc]] - submitted 2019sep23 * [[nlnet_2019_wishbone_streaming]] - submitted 2019sep26 -* [[nlnet_2019_standards]] - submitted 2019sep27 +* [[nlnet_2019_standards]] - submitted 2019sep27 - submitter found (phcomp) # MESA RADV Discussion links diff --git a/resources.mdwn b/resources.mdwn index ba4b5b694..e5a46b09f 100644 --- a/resources.mdwn +++ b/resources.mdwn @@ -4,6 +4,13 @@ This page aims to collect all the resources and specifications we need in one place for quick access. We will try our best to keep links here up-to-date. Feel free to add more links here. +# Libre-RISC-V Standards + +This list auto-generated from a page tag "standards": + +[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]] + + # RISC-V Instruction Set Architecture The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 8e6bbc27e..09cbf340c 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Simple-V (Parallelism Extension Proposal) Specification (Abridged) * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn index 8d8941bca..d4a69b352 100644 --- a/simple_v_extension/appendix.mdwn +++ b/simple_v_extension/appendix.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Simple-V (Parallelism Extension Proposal) Appendix * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index dea2ffd36..fa86b961d 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Simple-V (Parallelism Extension Proposal) Specification * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn index b822e697c..6b78aa198 100644 --- a/simple_v_extension/specification/bitmanip.mdwn +++ b/simple_v_extension/specification/bitmanip.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Bitmanip opcodes These are bit manipulation opcodes that, if provided, augment SimpleV for diff --git a/simple_v_extension/specification/mv.x.rst b/simple_v_extension/specification/mv.x.rst index 49d9144b3..bd668abaa 100644 --- a/simple_v_extension/specification/mv.x.rst +++ b/simple_v_extension/specification/mv.x.rst @@ -1,3 +1,5 @@ +[[!tag standards]] + MV.X and MV.swizzle =================== diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn index 80d6296c5..a7eea7a98 100644 --- a/simple_v_extension/specification/sv.setvl.mdwn +++ b/simple_v_extension/specification/sv.setvl.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # SV setvl sv.setvl allows optional setting of both MVL and of indirectly marking diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst index 6e67b1ca3..8260fee9e 100644 --- a/simple_v_extension/sv_prefix_proposal.rst +++ b/simple_v_extension/sv_prefix_proposal.rst @@ -1,3 +1,5 @@ +[[!tag standards]] + SimpleV Prefix (SVprefix) Proposal v0.3 ======================================= diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn index 413dcd5dc..c996b3955 100644 --- a/simple_v_extension/vblock_format.mdwn +++ b/simple_v_extension/vblock_format.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Simple-V (Parallelism Extension Proposal) Vector Block Format * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn index 0367f5c56..aa4b3f001 100644 --- a/simple_v_extension/vector_ops.mdwn +++ b/simple_v_extension/vector_ops.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Vector Operations Extension to SV This extension is usually dependent on SV SUBVL being implemented. When SUBVL is set to define the length of a subvector the operations in this extension interpret the elements as a single vector. diff --git a/zfpacc_proposal.mdwn b/zfpacc_proposal.mdwn index 96cdc8e2f..4262c53f9 100644 --- a/zfpacc_proposal.mdwn +++ b/zfpacc_proposal.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # FP Accuracy proposal Credits: diff --git a/ztrans_proposal.mdwn b/ztrans_proposal.mdwn index 5e2685850..ac805a542 100644 --- a/ztrans_proposal.mdwn +++ b/ztrans_proposal.mdwn @@ -1,3 +1,5 @@ +[[!tag standards]] + # Zftrans - transcendental operations Summary: -- 2.30.2