From 911e065e74368b45ab337ba8b24392290f4cee11 Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:16:54 +0530 Subject: [PATCH] arch-power: Fix precedence of register operands When RS and RA are both used as operands by an instruction, RS takes precedence over RA. In such cases, either both the register operands are used as sources or RS is a source and RA is a destination. This changes the order by giving RS the highest precedence and will be useful for proper disassembly generation. Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a Signed-off-by: Sandipan Das --- src/arch/power/isa/operands.isa | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index af89a625b..017469a01 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -41,9 +41,9 @@ def operand_types {{ def operands {{ # General Purpose Integer Reg Operands - 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1), - 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2), - 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3), + 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1), + 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2), + 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3), 'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4), # General Purpose Floating Point Reg Operands -- 2.30.2