From 9125a43f624653e6238dbb8713658cae2c5d43cd Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2018 04:58:50 -0700 Subject: [PATCH] arm: Use little endian packet accessors. We know data is little endian, so we can use those accessors explicitly. Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45 Reviewed-on: https://gem5-review.googlesource.com/c/13457 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/dev/arm/a9scu.cc | 4 +-- src/dev/arm/amba_device.cc | 2 +- src/dev/arm/amba_fake.cc | 2 +- src/dev/arm/energy_ctrl.cc | 6 ++--- src/dev/arm/generic_timer.cc | 6 ++--- src/dev/arm/gic_v2.cc | 16 ++++++------ src/dev/arm/gic_v2m.cc | 8 +++--- src/dev/arm/gpu_nomali.cc | 4 +-- src/dev/arm/hdlcd.cc | 4 +-- src/dev/arm/kmi.cc | 2 +- src/dev/arm/pl011.cc | 16 ++++++------ src/dev/arm/pl111.cc | 16 ++++++------ src/dev/arm/rtc_pl031.cc | 16 ++++++------ src/dev/arm/rv_ctrl.cc | 46 +++++++++++++++++----------------- src/dev/arm/timer_a9global.cc | 26 +++++++++---------- src/dev/arm/timer_cpulocal.cc | 32 ++++++++++++------------ src/dev/arm/timer_sp804.cc | 24 ++++++++++-------- src/dev/arm/ufs_device.cc | 8 +++--- src/dev/arm/vgic.cc | 47 +++++++++++++++++++---------------- src/dev/arm/vio_mmio.cc | 6 ++--- 20 files changed, 148 insertions(+), 143 deletions(-) diff --git a/src/dev/arm/a9scu.cc b/src/dev/arm/a9scu.cc index 86a50ae8e..677101b36 100644 --- a/src/dev/arm/a9scu.cc +++ b/src/dev/arm/a9scu.cc @@ -59,7 +59,7 @@ A9SCU::read(PacketPtr pkt) switch(daddr) { case Control: - pkt->set(1); // SCU already enabled + pkt->setLE(1); // SCU already enabled break; case Config: /* Without making a completely new SCU, we can use the core count field @@ -75,7 +75,7 @@ A9SCU::read(PacketPtr pkt) int smp_bits, core_cnt; smp_bits = power(2,sys->numContexts()) - 1; core_cnt = sys->numContexts() - 1; - pkt->set(smp_bits << 4 | core_cnt); + pkt->setLE(smp_bits << 4 | core_cnt); break; default: // Only configuration register is implemented diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc index d9acc9a00..a8404a42c 100644 --- a/src/dev/arm/amba_device.cc +++ b/src/dev/arm/amba_device.cc @@ -83,6 +83,6 @@ AmbaDevice::readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr) (amba_id >> byte) & 0xFF, pkt->getAddr() - pio_addr, byte); assert(pkt->getSize() == 4); - pkt->set((amba_id >> byte) & 0xFF); + pkt->setLE((amba_id >> byte) & 0xFF); return true; } diff --git a/src/dev/arm/amba_fake.cc b/src/dev/arm/amba_fake.cc index 475ff768a..9c14140fb 100644 --- a/src/dev/arm/amba_fake.cc +++ b/src/dev/arm/amba_fake.cc @@ -61,7 +61,7 @@ AmbaFake::read(PacketPtr pkt) DPRINTF(AMBA, " read register %#x\n", daddr); - pkt->set(0); + pkt->setLE(0); if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access) panic("Tried to read AmbaFake at offset %#x that doesn't exist\n", daddr); diff --git a/src/dev/arm/energy_ctrl.cc b/src/dev/arm/energy_ctrl.cc index 9cfce3a48..ba2d3e942 100644 --- a/src/dev/arm/energy_ctrl.cc +++ b/src/dev/arm/energy_ctrl.cc @@ -72,7 +72,7 @@ EnergyCtrl::read(PacketPtr pkt) if (!dvfsHandler->isEnabled()) { // NB: Zero is a good response if the handler is disabled - pkt->set(0); + pkt->setLE(0); warn_once("EnergyCtrl: Disabled handler, ignoring read from reg %i\n", reg); DPRINTF(EnergyCtrl, "dvfs handler disabled, return 0 for read from "\ @@ -141,7 +141,7 @@ EnergyCtrl::read(PacketPtr pkt) panic("Tried to read EnergyCtrl at offset %#x / reg %i\n", daddr, reg); } - pkt->set(result); + pkt->setLE(result); pkt->makeAtomicResponse(); return pioDelay; } @@ -153,7 +153,7 @@ EnergyCtrl::write(PacketPtr pkt) assert(pkt->getSize() == 4); uint32_t data; - data = pkt->get(); + data = pkt->getLE(); Addr daddr = pkt->getAddr() - pioAddr; assert((daddr & 3) == 0); diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc index 92c39c2ae..0994f6dd4 100644 --- a/src/dev/arm/generic_timer.cc +++ b/src/dev/arm/generic_timer.cc @@ -583,9 +583,9 @@ GenericTimerMem::read(PacketPtr pkt) DPRINTF(Timer, "Read 0x%x <- 0x%x(%i)\n", value, addr, size); if (size == 8) { - pkt->set(value); + pkt->setLE(value); } else if (size == 4) { - pkt->set(value); + pkt->setLE(value); } else { panic("Unexpected access size: %i\n", size); } @@ -602,7 +602,7 @@ GenericTimerMem::write(PacketPtr pkt) const Addr addr(pkt->getAddr()); const uint64_t value(size == 8 ? - pkt->get() : pkt->get()); + pkt->getLE() : pkt->getLE()); DPRINTF(Timer, "Write 0x%x -> 0x%x(%i)\n", value, addr, size); if (ctrlRange.contains(addr)) { diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 99124b08c..a24e56391 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -145,13 +145,13 @@ GicV2::readDistributor(PacketPtr pkt) switch (pkt->getSize()) { case 1: - pkt->set(resp); + pkt->setLE(resp); break; case 2: - pkt->set(resp); + pkt->setLE(resp); break; case 4: - pkt->set(resp); + pkt->setLE(resp); break; default: panic("Invalid size while reading Distributor regs in GIC: %d\n", @@ -296,7 +296,7 @@ GicV2::readCpu(PacketPtr pkt) DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr, ctx); - pkt->set(readCpu(ctx, daddr)); + pkt->setLE(readCpu(ctx, daddr)); pkt->makeAtomicResponse(); return cpuPioDelay; @@ -395,13 +395,13 @@ GicV2::writeDistributor(PacketPtr pkt) switch (data_sz) { case 1: - pkt_data = pkt->get(); + pkt_data = pkt->getLE(); break; case 2: - pkt_data = pkt->get(); + pkt_data = pkt->getLE(); break; case 4: - pkt_data = pkt->get(); + pkt_data = pkt->getLE(); break; default: panic("Invalid size when writing to priority regs in Gic: %d\n", @@ -558,7 +558,7 @@ GicV2::writeCpu(PacketPtr pkt) assert(pkt->req->hasContextId()); const ContextID ctx = pkt->req->contextId(); - const uint32_t data = pkt->get(); + const uint32_t data = pkt->getLE(); DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n", ctx, daddr, data); diff --git a/src/dev/arm/gic_v2m.cc b/src/dev/arm/gic_v2m.cc index d90cb986e..9ae0f68ee 100644 --- a/src/dev/arm/gic_v2m.cc +++ b/src/dev/arm/gic_v2m.cc @@ -114,18 +114,18 @@ Gicv2m::read(PacketPtr pkt) switch (offset) { case MSI_TYPER: - pkt->set((frames[frame]->spi_base << 16) | + pkt->setLE((frames[frame]->spi_base << 16) | frames[frame]->spi_len); break; case PER_ID4: - pkt->set(0x4 | ((4+log2framenum) << 4)); + pkt->setLE(0x4 | ((4+log2framenum) << 4)); // Nr of 4KB blocks used by component. This is messy as frames are 64K // (16, ie 2^4) and we should assert we're given a Po2 number of frames. break; default: DPRINTF(GICV2M, "GICv2m: Read of unk reg %#x\n", offset); - pkt->set(0); + pkt->setLE(0); }; pkt->makeAtomicResponse(); @@ -144,7 +144,7 @@ Gicv2m::write(PacketPtr pkt) if (offset == MSI_SETSPI_NSR) { /* Is payload SPI number within range? */ - uint32_t m = pkt->get(); + uint32_t m = pkt->getLE(); if (m >= frames[frame]->spi_base && m < (frames[frame]->spi_base + frames[frame]->spi_len)) { DPRINTF(GICV2M, "GICv2m: Frame %d raising MSI %d\n", frame, m); diff --git a/src/dev/arm/gpu_nomali.cc b/src/dev/arm/gpu_nomali.cc index a6c3e29e5..c8630c707 100644 --- a/src/dev/arm/gpu_nomali.cc +++ b/src/dev/arm/gpu_nomali.cc @@ -160,7 +160,7 @@ NoMaliGpu::read(PacketPtr pkt) else if (addr & 0x3) panic("Unaligned GPU read: %i\n", size); - pkt->set(readReg(addr)); + pkt->setLE(readReg(addr)); pkt->makeResponse(); return 0; @@ -181,7 +181,7 @@ NoMaliGpu::write(PacketPtr pkt) else if (addr & 0x3) panic("Unaligned GPU write: %i\n", size); - writeReg(addr, pkt->get()); + writeReg(addr, pkt->getLE()); pkt->makeAtomicResponse(); return 0; diff --git a/src/dev/arm/hdlcd.cc b/src/dev/arm/hdlcd.cc index 20dc7d44e..113c1c358 100644 --- a/src/dev/arm/hdlcd.cc +++ b/src/dev/arm/hdlcd.cc @@ -248,7 +248,7 @@ HDLcd::read(PacketPtr pkt) const uint32_t data(readReg(daddr)); DPRINTF(HDLcd, "read register 0x%04x: 0x%x\n", daddr, data); - pkt->set(data); + pkt->setLE(data); pkt->makeAtomicResponse(); return pioDelay; } @@ -264,7 +264,7 @@ HDLcd::write(PacketPtr pkt) panic_if(pkt->getSize() != 4, "Unhandled read size (address: 0x.4x, size: %u)", daddr, pkt->getSize()); - const uint32_t data(pkt->get()); + const uint32_t data(pkt->getLE()); DPRINTF(HDLcd, "write register 0x%04x: 0x%x\n", daddr, data); writeReg(daddr, data); diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc index 8055afe2e..3cb598d68 100644 --- a/src/dev/arm/kmi.cc +++ b/src/dev/arm/kmi.cc @@ -98,7 +98,7 @@ Pl050::read(PacketPtr pkt) default: if (readId(pkt, ambaId, pioAddr)) { // Hack for variable size accesses - data = pkt->get(); + data = pkt->getLE(); break; } diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc index 5ca9f6087..fe73d9674 100644 --- a/src/dev/arm/pl011.cc +++ b/src/dev/arm/pl011.cc @@ -136,7 +136,7 @@ Pl011::read(PacketPtr pkt) default: if (readId(pkt, AMBA_ID, pioAddr)) { // Hack for variable size accesses - data = pkt->get(); + data = pkt->getLE(); break; } @@ -146,13 +146,13 @@ Pl011::read(PacketPtr pkt) switch(pkt->getSize()) { case 1: - pkt->set(data); + pkt->setLE(data); break; case 2: - pkt->set(data); + pkt->setLE(data); break; case 4: - pkt->set(data); + pkt->setLE(data); break; default: panic("Uart read size too big?\n"); @@ -173,7 +173,7 @@ Pl011::write(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, - pkt->get(), pkt->getSize()); + pkt->getLE(), pkt->getSize()); // use a temporary data since the uart registers are read/written with // different size operations @@ -182,13 +182,13 @@ Pl011::write(PacketPtr pkt) switch(pkt->getSize()) { case 1: - data = pkt->get(); + data = pkt->getLE(); break; case 2: - data = pkt->get(); + data = pkt->getLE(); break; case 4: - data = pkt->get(); + data = pkt->getLE(); break; default: panic("Uart write size too big?\n"); diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc index 344eb0864..7560ec4b9 100644 --- a/src/dev/arm/pl111.cc +++ b/src/dev/arm/pl111.cc @@ -185,7 +185,7 @@ Pl111::read(PacketPtr pkt) default: if (readId(pkt, AMBA_ID, pioAddr)) { // Hack for variable size accesses - data = pkt->get(); + data = pkt->getLE(); break; } else if (daddr >= CrsrImage && daddr <= 0xBFC) { // CURSOR IMAGE @@ -208,13 +208,13 @@ Pl111::read(PacketPtr pkt) switch(pkt->getSize()) { case 1: - pkt->set(data); + pkt->setLE(data); break; case 2: - pkt->set(data); + pkt->setLE(data); break; case 4: - pkt->set(data); + pkt->setLE(data); break; default: panic("CLCD controller read size too big?\n"); @@ -236,13 +236,13 @@ Pl111::write(PacketPtr pkt) switch(pkt->getSize()) { case 1: - data = pkt->get(); + data = pkt->getLE(); break; case 2: - data = pkt->get(); + data = pkt->getLE(); break; case 4: - data = pkt->get(); + data = pkt->getLE(); break; default: panic("PL111 CLCD controller write size too big?\n"); @@ -255,7 +255,7 @@ Pl111::write(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr, - pkt->get(), pkt->getSize()); + pkt->getLE(), pkt->getSize()); switch (daddr) { case LcdTiming0: diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc index 5b6ce5288..9abb77629 100644 --- a/src/dev/arm/rtc_pl031.cc +++ b/src/dev/arm/rtc_pl031.cc @@ -92,7 +92,7 @@ PL031::read(PacketPtr pkt) default: if (readId(pkt, ambaId, pioAddr)) { // Hack for variable sized access - data = pkt->get(); + data = pkt->getLE(); break; } panic("Tried to read PL031 at offset %#x that doesn't exist\n", daddr); @@ -101,13 +101,13 @@ PL031::read(PacketPtr pkt) switch(pkt->getSize()) { case 1: - pkt->set(data); + pkt->setLE(data); break; case 2: - pkt->set(data); + pkt->setLE(data); break; case 4: - pkt->set(data); + pkt->setLE(data); break; default: panic("Uart read size too big?\n"); @@ -131,22 +131,22 @@ PL031::write(PacketPtr pkt) case DataReg: break; case MatchReg: - matchVal = pkt->get(); + matchVal = pkt->getLE(); resyncMatch(); break; case LoadReg: lastWrittenTick = curTick(); - timeVal = pkt->get(); + timeVal = pkt->getLE(); loadVal = timeVal; resyncMatch(); break; case ControlReg: break; // Can't stop when started case IntMask: - maskInt = pkt->get(); + maskInt = pkt->getLE(); break; case IntClear: - if (pkt->get()) { + if (pkt->getLE()) { rawInt = false; pendingInt = false; } diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc index 954be6597..9f9e51f09 100644 --- a/src/dev/arm/rv_ctrl.cc +++ b/src/dev/arm/rv_ctrl.cc @@ -61,66 +61,66 @@ RealViewCtrl::read(PacketPtr pkt) switch(daddr) { case ProcId0: - pkt->set(params()->proc_id0); + pkt->setLE(params()->proc_id0); break; case ProcId1: - pkt->set(params()->proc_id1); + pkt->setLE(params()->proc_id1); break; case Clock24: Tick clk; clk = SimClock::Float::MHz * curTick() * 24; - pkt->set((uint32_t)(clk)); + pkt->setLE((uint32_t)(clk)); break; case Clock100: Tick clk100; clk100 = SimClock::Float::MHz * curTick() * 100; - pkt->set((uint32_t)(clk100)); + pkt->setLE((uint32_t)(clk100)); break; case Flash: - pkt->set(0); + pkt->setLE(0); break; case Clcd: - pkt->set(0x00001F00); + pkt->setLE(0x00001F00); break; case Osc0: - pkt->set(0x00012C5C); + pkt->setLE(0x00012C5C); break; case Osc1: - pkt->set(0x00002CC0); + pkt->setLE(0x00002CC0); break; case Osc2: - pkt->set(0x00002C75); + pkt->setLE(0x00002C75); break; case Osc3: - pkt->set(0x00020211); + pkt->setLE(0x00020211); break; case Osc4: - pkt->set(0x00002C75); + pkt->setLE(0x00002C75); break; case Lock: - pkt->set(sysLock); + pkt->setLE(sysLock); break; case Flags: - pkt->set(flags); + pkt->setLE(flags); break; case IdReg: - pkt->set(params()->idreg); + pkt->setLE(params()->idreg); break; case CfgStat: - pkt->set(1); + pkt->setLE(1); break; case CfgData: - pkt->set(scData); + pkt->setLE(scData); DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData); break; case CfgCtrl: - pkt->set(0); // not busy + pkt->setLE(0); // not busy DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n"); break; default: warn("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr); - pkt->set(0); + pkt->setLE(0); break; } pkt->makeAtomicResponse(); @@ -144,26 +144,26 @@ RealViewCtrl::write(PacketPtr pkt) case Osc4: break; case Lock: - sysLock.lockVal = pkt->get(); + sysLock.lockVal = pkt->getLE(); break; case ResetCtl: // Ignore writes to reset control warn_once("Ignoring write to reset control\n"); break; case Flags: - flags = pkt->get(); + flags = pkt->getLE(); break; case FlagsClr: flags = 0; break; case CfgData: - scData = pkt->get(); + scData = pkt->getLE(); break; case CfgCtrl: { // A request is being submitted to read/write the system control // registers. See // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html - CfgCtrlReg req = pkt->get(); + CfgCtrlReg req = pkt->getLE(); if (!req.start) { DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n", req); @@ -195,7 +195,7 @@ RealViewCtrl::write(PacketPtr pkt) case CfgStat: // Weird to write this default: warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n", - daddr, pkt->get()); + daddr, pkt->getLE()); break; } pkt->makeAtomicResponse(); diff --git a/src/dev/arm/timer_a9global.cc b/src/dev/arm/timer_a9global.cc index 742ed76cd..1d4089f7f 100644 --- a/src/dev/arm/timer_a9global.cc +++ b/src/dev/arm/timer_a9global.cc @@ -94,19 +94,19 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr) case CounterRegLow32: time = getTimeCounterFromTicks(curTick()); DPRINTF(Timer, "-- returning lower 32-bits of counter: %u\n", time); - pkt->set(time); + pkt->setLE(time); break; case CounterRegHigh32: time = getTimeCounterFromTicks(curTick()); time >>= 32; DPRINTF(Timer, "-- returning upper 32-bits of counter: %u\n", time); - pkt->set(time); + pkt->setLE(time); break; case ControlReg: - pkt->set(control); + pkt->setLE(control); break; case IntStatusReg: - pkt->set(rawInt); + pkt->setLE(rawInt); break; case CmpValRegLow32: DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n", @@ -117,7 +117,7 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr) time = 0; } DPRINTF(Timer, "-- returning lower 32-bits of comparator: %u\n", time); - pkt->set(time); + pkt->setLE(time); break; case CmpValRegHigh32: DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n", @@ -129,17 +129,17 @@ A9GlobalTimer::Timer::read(PacketPtr pkt, Addr daddr) time = 0; } DPRINTF(Timer, "-- returning upper 32-bits of comparator: %u\n", time); - pkt->set(time); + pkt->setLE(time); break; case AutoIncrementReg: - pkt->set(autoIncValue); + pkt->setLE(autoIncValue); break; default: panic("Tried to read A9GlobalTimer at offset %#x\n", daddr); break; } DPRINTF(Timer, "Reading %#x from A9GlobalTimer at offset: %#x\n", - pkt->get(), daddr); + pkt->getLE(), daddr); } Tick @@ -165,7 +165,7 @@ void A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr) { DPRINTF(Timer, "Writing %#x to A9GlobalTimer at offset: %#x\n", - pkt->get(), daddr); + pkt->getLE(), daddr); switch (daddr) { case CounterRegLow32: case CounterRegHigh32: @@ -176,7 +176,7 @@ A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr) bool old_cmpEnable; old_enable = control.enable; old_cmpEnable = control.cmpEnable; - control = pkt->get(); + control = pkt->getLE(); if ((old_enable == 0) && control.enable) restartCounter(); if ((old_cmpEnable == 0) && control.cmpEnable) @@ -193,14 +193,14 @@ A9GlobalTimer::Timer::write(PacketPtr pkt, Addr daddr) break; case CmpValRegLow32: cmpVal &= 0xFFFFFFFF00000000ULL; - cmpVal |= (uint64_t)pkt->get(); + cmpVal |= (uint64_t)pkt->getLE(); break; case CmpValRegHigh32: cmpVal &= 0x00000000FFFFFFFFULL; - cmpVal |= ((uint64_t)pkt->get() << 32); + cmpVal |= ((uint64_t)pkt->getLE() << 32); break; case AutoIncrementReg: - autoIncValue = pkt->get(); + autoIncValue = pkt->getLE(); break; default: panic("Tried to write A9GlobalTimer at offset %#x\n", daddr); diff --git a/src/dev/arm/timer_cpulocal.cc b/src/dev/arm/timer_cpulocal.cc index 9e9946b1f..a0825232f 100644 --- a/src/dev/arm/timer_cpulocal.cc +++ b/src/dev/arm/timer_cpulocal.cc @@ -116,7 +116,7 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr) switch(daddr) { case TimerLoadReg: - pkt->set(timerLoadValue); + pkt->setLE(timerLoadValue); break; case TimerCounterReg: DPRINTF(Timer, "Event schedule for timer %d, clock=%d, prescale=%d\n", @@ -126,16 +126,16 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr) time = time / parent->clockPeriod() / power(16, timerControl.prescalar); DPRINTF(Timer, "-- returning counter at %d\n", time); - pkt->set(time); + pkt->setLE(time); break; case TimerControlReg: - pkt->set(timerControl); + pkt->setLE(timerControl); break; case TimerIntStatusReg: - pkt->set(rawIntTimer); + pkt->setLE(rawIntTimer); break; case WatchdogLoadReg: - pkt->set(watchdogLoadValue); + pkt->setLE(watchdogLoadValue); break; case WatchdogCounterReg: DPRINTF(Timer, @@ -146,16 +146,16 @@ CpuLocalTimer::Timer::read(PacketPtr pkt, Addr daddr) time = time / parent->clockPeriod() / power(16, watchdogControl.prescalar); DPRINTF(Timer, "-- returning counter at %d\n", time); - pkt->set(time); + pkt->setLE(time); break; case WatchdogControlReg: - pkt->set(watchdogControl); + pkt->setLE(watchdogControl); break; case WatchdogIntStatusReg: - pkt->set(rawIntWatchdog); + pkt->setLE(rawIntWatchdog); break; case WatchdogResetStatusReg: - pkt->set(rawResetWatchdog); + pkt->setLE(rawResetWatchdog); break; case WatchdogDisableReg: panic("Tried to read from WatchdogDisableRegister\n"); @@ -197,16 +197,16 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr) case TimerLoadReg: // Writing to this register also resets the counter register and // starts decrementing if the counter is enabled. - timerLoadValue = pkt->get(); + timerLoadValue = pkt->getLE(); restartTimerCounter(timerLoadValue); break; case TimerCounterReg: // Can be written, doesn't start counting unless the timer is enabled - restartTimerCounter(pkt->get()); + restartTimerCounter(pkt->getLE()); break; case TimerControlReg: old_enable = timerControl.enable; - timerControl = pkt->get(); + timerControl = pkt->getLE(); if ((old_enable == 0) && timerControl.enable) restartTimerCounter(timerLoadValue); break; @@ -218,19 +218,19 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr) } break; case WatchdogLoadReg: - watchdogLoadValue = pkt->get(); + watchdogLoadValue = pkt->getLE(); restartWatchdogCounter(watchdogLoadValue); break; case WatchdogCounterReg: // Can't be written when in watchdog mode, but can in timer mode if (!watchdogControl.watchdogMode) { - restartWatchdogCounter(pkt->get()); + restartWatchdogCounter(pkt->getLE()); } break; case WatchdogControlReg: old_enable = watchdogControl.enable; old_wd_mode = watchdogControl.watchdogMode; - watchdogControl = pkt->get(); + watchdogControl = pkt->getLE(); if ((old_enable == 0) && watchdogControl.enable) restartWatchdogCounter(watchdogLoadValue); // cannot disable watchdog using control register @@ -250,7 +250,7 @@ CpuLocalTimer::Timer::write(PacketPtr pkt, Addr daddr) break; case WatchdogDisableReg: old_val = watchdogDisableReg; - watchdogDisableReg = pkt->get(); + watchdogDisableReg = pkt->getLE(); // if this sequence is observed, turn off watchdog mode if (old_val == 0x12345678 && watchdogDisableReg == 0x87654321) watchdogControl.watchdogMode = 0; diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc index f28ba7bf0..0549c6318 100644 --- a/src/dev/arm/timer_sp804.cc +++ b/src/dev/arm/timer_sp804.cc @@ -86,7 +86,7 @@ Sp804::Timer::read(PacketPtr pkt, Addr daddr) { switch(daddr) { case LoadReg: - pkt->set(loadValue); + pkt->setLE(loadValue); break; case CurrentReg: DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n", @@ -95,25 +95,26 @@ Sp804::Timer::read(PacketPtr pkt, Addr daddr) time = zeroEvent.when() - curTick(); time = time / clock / power(16, control.timerPrescale); DPRINTF(Timer, "-- returning counter at %d\n", time); - pkt->set(time); + pkt->setLE(time); break; case ControlReg: - pkt->set(control); + pkt->setLE(control); break; case RawISR: - pkt->set(rawInt); + pkt->setLE(rawInt); break; case MaskedISR: - pkt->set(pendingInt); + pkt->setLE(pendingInt); break; case BGLoad: - pkt->set(loadValue); + pkt->setLE(loadValue); break; default: panic("Tried to read SP804 timer at offset %#x\n", daddr); break; } - DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", pkt->get(), daddr); + DPRINTF(Timer, "Reading %#x from Timer at offset: %#x\n", + pkt->getLE(), daddr); } Tick @@ -137,10 +138,11 @@ Sp804::write(PacketPtr pkt) void Sp804::Timer::write(PacketPtr pkt, Addr daddr) { - DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", pkt->get(), daddr); + DPRINTF(Timer, "Writing %#x to Timer at offset: %#x\n", + pkt->getLE(), daddr); switch (daddr) { case LoadReg: - loadValue = pkt->get(); + loadValue = pkt->getLE(); restartCounter(loadValue); break; case CurrentReg: @@ -149,7 +151,7 @@ Sp804::Timer::write(PacketPtr pkt, Addr daddr) case ControlReg: bool old_enable; old_enable = control.timerEnable; - control = pkt->get(); + control = pkt->getLE(); if ((old_enable == 0) && control.timerEnable) restartCounter(loadValue); break; @@ -162,7 +164,7 @@ Sp804::Timer::write(PacketPtr pkt, Addr daddr) } break; case BGLoad: - loadValue = pkt->get(); + loadValue = pkt->getLE(); break; default: panic("Tried to write SP804 timer at offset %#x\n", daddr); diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc index 137ad8c27..cc2800072 100644 --- a/src/dev/arm/ufs_device.cc +++ b/src/dev/arm/ufs_device.cc @@ -1053,7 +1053,7 @@ UFSHostDevice::read(PacketPtr pkt) break; } - pkt->set(data); + pkt->setLE(data); pkt->makeResponse(); return pioDelay; } @@ -1071,15 +1071,15 @@ UFSHostDevice::write(PacketPtr pkt) switch (pkt->getSize()) { case 1: - data = pkt->get(); + data = pkt->getLE(); break; case 2: - data = pkt->get(); + data = pkt->getLE(); break; case 4: - data = pkt->get(); + data = pkt->getLE(); break; default: diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc index 529520403..3e295828c 100644 --- a/src/dev/arm/vgic.cc +++ b/src/dev/arm/vgic.cc @@ -106,16 +106,16 @@ VGic::readVCpu(PacketPtr pkt) switch (daddr) { case GICV_CTLR: - pkt->set(vid->vctrl); + pkt->setLE(vid->vctrl); break; case GICV_IAR: { int i = findHighestPendingLR(vid); if (i < 0 || !vid->vctrl.En) { - pkt->set(1023); // "No int" marker + pkt->setLE(1023); // "No int" marker } else { ListReg *lr = &vid->LR[i]; - pkt->set(lr->VirtualID | + pkt->setLE(lr->VirtualID | (((int)lr->CpuID) << 10)); // We don't support auto-EOI of HW interrupts via real GIC! // Fortunately, KVM doesn't use this. How about Xen...? Ulp! @@ -160,15 +160,15 @@ VGic::readCtrl(PacketPtr pkt) switch (daddr) { case GICH_HCR: - pkt->set(vid->hcr); + pkt->setLE(vid->hcr); break; case GICH_VTR: - pkt->set(0x44000000 | (NUM_LR - 1)); + pkt->setLE(0x44000000 | (NUM_LR - 1)); break; case GICH_VMCR: - pkt->set( + pkt->setLE( ((uint32_t)vid->VMPriMask << 27) | ((uint32_t)vid->VMBP << 21) | ((uint32_t)vid->VMABP << 18) | @@ -182,15 +182,15 @@ VGic::readCtrl(PacketPtr pkt) break; case GICH_MISR: - pkt->set(getMISR(vid)); + pkt->setLE(getMISR(vid)); break; case GICH_EISR0: - pkt->set(vid->eisr & 0xffffffff); + pkt->setLE(vid->eisr & 0xffffffff); break; case GICH_EISR1: - pkt->set(vid->eisr >> 32); + pkt->setLE(vid->eisr >> 32); break; case GICH_ELSR0: { @@ -199,7 +199,7 @@ VGic::readCtrl(PacketPtr pkt) if (!vid->LR[i].State) bm |= 1 << i; } - pkt->set(bm); + pkt->setLE(bm); } break; case GICH_ELSR1: { @@ -208,19 +208,19 @@ VGic::readCtrl(PacketPtr pkt) if (!vid->LR[i].State) bm |= 1 << (i-32); } - pkt->set(bm); + pkt->setLE(bm); } break; case GICH_APR0: warn_once("VGIC GICH_APR read!\n"); - pkt->set(0); + pkt->setLE(0); break; case GICH_LR0: case GICH_LR1: case GICH_LR2: case GICH_LR3: - pkt->set(vid->LR[(daddr - GICH_LR0) >> 2]); + pkt->setLE(vid->LR[(daddr - GICH_LR0) >> 2]); break; default: @@ -240,20 +240,21 @@ VGic::writeVCpu(PacketPtr pkt) assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; - DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", daddr, pkt->get()); + DPRINTF(VGIC, "VGIC VCPU write register %#x <= %#x\n", + daddr, pkt->getLE()); switch (daddr) { case GICV_CTLR: - vid->vctrl = pkt->get(); + vid->vctrl = pkt->getLE(); break; case GICV_PMR: - vid->VMPriMask = pkt->get(); + vid->VMPriMask = pkt->getLE(); break; case GICV_EOIR: { // We don't handle the split EOI-then-DIR mode. Linux (guest) // doesn't need it though. assert(!vid->vctrl.EOImode); - uint32_t w = pkt->get(); + uint32_t w = pkt->getLE(); unsigned int virq = w & 0x3ff; unsigned int vcpu = (w >> 10) & 7; int i = findLRForVIRQ(vid, virq, vcpu); @@ -268,7 +269,8 @@ VGic::writeVCpu(PacketPtr pkt) } } break; default: - panic("VGIC VCPU write %#x to unk address %#x\n", pkt->get(), daddr); + panic("VGIC VCPU write %#x to unk address %#x\n", + pkt->getLE(), daddr); } // This updates the EISRs and flags IRQs: @@ -285,7 +287,8 @@ VGic::writeCtrl(PacketPtr pkt) ContextID ctx_id = pkt->req->contextId(); - DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get()); + DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", + daddr, pkt->getLE()); /* Munge the address: 0-0xfff is the usual space banked by requester CPU. * Anything > that is 0x200-sized slices of 'per CPU' regs. @@ -301,12 +304,12 @@ VGic::writeCtrl(PacketPtr pkt) switch (daddr) { case GICH_HCR: - vid->hcr = pkt->get(); + vid->hcr = pkt->getLE(); // update int state break; case GICH_VMCR: { - uint32_t d = pkt->get(); + uint32_t d = pkt->getLE(); vid->VMPriMask = d >> 27; vid->VMBP = (d >> 21) & 7; vid->VMABP = (d >> 18) & 7; @@ -326,7 +329,7 @@ VGic::writeCtrl(PacketPtr pkt) case GICH_LR1: case GICH_LR2: case GICH_LR3: - vid->LR[(daddr - GICH_LR0) >> 2] = pkt->get(); + vid->LR[(daddr - GICH_LR0) >> 2] = pkt->getLE(); // update int state break; diff --git a/src/dev/arm/vio_mmio.cc b/src/dev/arm/vio_mmio.cc index 9f7bf1333..b9ecce918 100644 --- a/src/dev/arm/vio_mmio.cc +++ b/src/dev/arm/vio_mmio.cc @@ -79,7 +79,7 @@ MmioVirtIO::read(PacketPtr pkt) const uint32_t value = read(offset); DPRINTF(VIOIface, " value: 0x%x\n", value); pkt->makeResponse(); - pkt->set(value); + pkt->setLE(value); return 0; } @@ -173,9 +173,9 @@ MmioVirtIO::write(PacketPtr pkt) } panic_if(size != 4, "Unexpected write size @ 0x%x: %u\n", offset, size); - DPRINTF(VIOIface, " value: 0x%x\n", pkt->get()); + DPRINTF(VIOIface, " value: 0x%x\n", pkt->getLE()); pkt->makeResponse(); - write(offset, pkt->get()); + write(offset, pkt->getLE()); return 0; } -- 2.30.2