From 9129a561984472bfc7a076742ac7e3ee9117c197 Mon Sep 17 00:00:00 2001 From: Vladimir Makarov Date: Fri, 29 Sep 2017 17:39:58 +0000 Subject: [PATCH] re PR target/81481 (Spills %xmm to stack in glibc strspn SSE 4.2 variant) 2017-09-29 Vladimir Makarov PR target/81481 * ira-costs.c (scan_one_insn): Don't take into account PIC equiv with a symbol for LRA. 2017-09-29 Vladimir Makarov PR target/81481 * gcc.target/i386/pr81481.c: New. From-SVN: r253300 --- gcc/ChangeLog | 6 ++++++ gcc/ira-costs.c | 5 ++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr81481.c | 18 ++++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr81481.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a2eea908053..bdf728b6fff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-09-29 Vladimir Makarov + + PR target/81481 + * ira-costs.c (scan_one_insn): Don't take into account PIC equiv + with a symbol for LRA. + 2017-09-29 Vladimir Makarov PR rtl-optimization/82338 diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index 714bdbd8c70..0bd07788833 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1471,7 +1471,10 @@ scan_one_insn (rtx_insn *insn) && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)), XEXP (note, 0)) && REG_N_SETS (REGNO (SET_DEST (set))) == 1)) - && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))) + && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set))) + /* LRA does not use equiv with a symbol for PIC code. */ + && (! ira_use_lra_p || ! pic_offset_table_rtx + || ! contains_symbol_ref_p (XEXP (note, 0)))) { enum reg_class cl = GENERAL_REGS; rtx reg = SET_DEST (set); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 537b751f636..ac88fd3edf7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-09-29 Vladimir Makarov + + PR target/81481 + * gcc.target/i386/pr81481.c: New. + 2017-09-29 Kelvin Nilsen * gcc.target/powerpc/swaps-p8-30.c: Exchange the order of dg-do diff --git a/gcc/testsuite/gcc.target/i386/pr81481.c b/gcc/testsuite/gcc.target/i386/pr81481.c new file mode 100644 index 00000000000..a5b936fdacc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81481.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ssse3 } */ +/* { dg-options "-O2 -fpic -mssse3" } */ +/* { dg-final { scan-assembler-not "pshufb\[ \t\]\\(%esp\\)" } } */ +#include + +extern const signed char c[31] __attribute__((visibility("hidden"))); + +__m128i f(__m128i *x, void *v) +{ + int i; + asm("# %0" : "=r"(i)); + __m128i t = _mm_loadu_si128((void*)&c[i]); + __m128i xx = *x; + xx = _mm_shuffle_epi8(xx, t); + asm("# %0 %1 %2" : "+x"(xx) : "r"(c), "r"(i)); + return xx; +} -- 2.30.2