From 913ad2a5a9145b15284fb7899d3aad90dd7a005a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Jun 2021 11:09:54 +0000 Subject: [PATCH] add coresync_clk to list of HTree --- experiments10_verilog/doDesign.py | 1 + 1 file changed, 1 insertion(+) diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py index f7ee17d..74a5be1 100644 --- a/experiments10_verilog/doDesign.py +++ b/experiments10_verilog/doDesign.py @@ -85,6 +85,7 @@ def scriptMain ( **kw ): adderConf.chipConf.name = 'chip' #adderConf.chipConf.ioPadGauge = 'LibreSOCIO' adderConf.chipConf.ioPadGauge = 'niolib' + adderConf.useHTree('coresync_clk') adderConf.useHTree('jtag_tck_from_pad') adderConf.useHTree('sys_clk_from_pad') adderConf.coreSize = ( l(coreSize), l(coreSize) ) -- 2.30.2