From 9141a08403877e01c6cc40f384e1d27f2f7a6116 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 25 Nov 2021 17:07:05 +0100 Subject: [PATCH] add testcase for invalid pagetable --- src/soc/experiment/test/test_loadstore1.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py index 9c646b87..10d6a14d 100644 --- a/src/soc/experiment/test/test_loadstore1.py +++ b/src/soc/experiment/test/test_loadstore1.py @@ -100,6 +100,7 @@ def setup_mmu(): return m, cmpi test_exceptions = True +test_invalid = False def _test_loadstore1(dut, mem): mmu = dut.submodules.mmu @@ -107,6 +108,19 @@ def _test_loadstore1(dut, mem): global stop stop = False + if test_invalid: + print("=== test invalid ===") + # no process table for this test + yield mmu.rin.prtbl.eq(0) # set process table + yield + addr = 0 + ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1) + print("ld_data",ld_data,exc) + assert(exc=="slow") + invalid = yield pi.exc_o.invalid + assert(invalid==1) + print("=== test invalid done ===") + yield mmu.rin.prtbl.eq(0x1000000) # set process table yield -- 2.30.2