From 91619b1cd639f66137a9763f5f6d1cc1a044b380 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 17:25:51 +0100 Subject: [PATCH] annoying syntax error --- src/soc/fu/logical/main_stage.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index 1c7fcd75..41183b5b 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -118,9 +118,9 @@ class LogicalMainStage(PipeModBase): comb += a32.eq(a[0:32]) with m.If(op.is_32bit): - comb += cntz_i.eq(Mux(count_right, a32[::-1], a32) + comb += cntz_i.eq(Mux(count_right, a32[::-1], a32)) with m.Else(): - comb += cntz_i.eq(Mux(count_right, a[::-1], a) + comb += cntz_i.eq(Mux(count_right, a[::-1], a)) m.submodules.clz = clz = CLZ(64) comb += clz.sig_in.eq(cntz_i) -- 2.30.2