From 918041d4bd9e624fff76ea1616b578c3a5a1544c Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 23 Sep 2019 14:09:51 +0100
Subject: [PATCH]

---
 simple_v_extension/bigint_example.mdwn | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 simple_v_extension/bigint_example.mdwn

diff --git a/simple_v_extension/bigint_example.mdwn b/simple_v_extension/bigint_example.mdwn
new file mode 100644
index 000000000..d2673e32c
--- /dev/null
+++ b/simple_v_extension/bigint_example.mdwn
@@ -0,0 +1,23 @@
+    li t1, -1 # 0xfffffff...fff
+    VBLK.pred.t3 = {inv, t0}
+    VBLK.pred.t4 = {t0 }
+    VBLK.reg.a0 = {vec}
+    VBLK.reg.a1 = {vec}
+    VBLK.VL = 8
+    add t4, a0, a1
+    sub t3, x0, a1 # invert a1
+    BLT a0, t3, cont # stores tests in t0
+    ret
+
+    VBLK.pred.t1 = {inv, t0}
+    VBLK.pred.t4 = {t0 }
+    VBLK.reg.a0 = {vec}
+    VBLK.reg.a1 = {vec}
+    cont:
+    slli t0, 1 # shifts up carry by 1
+    addi t4, 1 # predicated on t0
+    BLT t4, t1, cont2 # tests into t0
+    ret
+    cont2:
+    j cont
+
-- 
2.30.2