From 9181c2ea16d384c57e6bb4e757ecaf1b52b8e7f1 Mon Sep 17 00:00:00 2001
From: Adrien Pesle <adrien.pesle@arm.com>
Date: Thu, 11 Oct 2018 16:09:07 +0200
Subject: [PATCH] dev-arm: Fix Gicv2 distributor group register

For each bit in GICD_IGROUPR:
value 0 means corresponding irq is group0
value 1 means corresponding irq is group 1.

Change-Id: I15699d4bc89ff3df0e0bdb41154c0d0989dc2f63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13555
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/dev/arm/gic_v2.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index c9c1a4715..4afad89f6 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -336,7 +336,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters
 
     bool isGroup0(ContextID ctx, uint32_t int_num) {
         const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
-        return bits(group_reg, intNumToBit(int_num));
+        return !bits(group_reg, intNumToBit(int_num));
     }
 
     /**
-- 
2.30.2