From 91951a9fd0aeb84f4599c56d88f651c9eb6ce21c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 Aug 2020 12:07:26 +0100 Subject: [PATCH] connect up a DMI FSM to litex sim --- src/soc/litex/florent/microwatt/core.py | 20 +++-- src/soc/litex/florent/sim.py | 113 +++++++++++++++++------- 2 files changed, 96 insertions(+), 37 deletions(-) diff --git a/src/soc/litex/florent/microwatt/core.py b/src/soc/litex/florent/microwatt/core.py index 704eb18f..344c7c6f 100644 --- a/src/soc/litex/florent/microwatt/core.py +++ b/src/soc/litex/florent/microwatt/core.py @@ -53,6 +53,13 @@ class Microwatt(CPU): self.periph_buses = [ibus, dbus] self.memory_buses = [] + self.dmi_addr = Signal(3) + self.dmi_din = Signal(64) + self.dmi_dout = Signal(64) + self.dmi_wr = Signal(1) + self.dmi_ack = Signal(1) + self.dmi_req = Signal(1) + # # # self.cpu_params = dict( @@ -84,13 +91,14 @@ class Microwatt(CPU): o_wishbone_data_sel = dbus.sel, o_wishbone_data_we = dbus.we, + # Debug bus - i_dmi_addr = 0, - i_dmi_din = 0, - #o_dmi_dout =, - i_dmi_req = 0, - i_dmi_wr = 0, - #o_dmi_ack =, + i_dmi_addr = self.dmi_addr, + i_dmi_din = self.dmi_din, + o_dmi_dout = self.dmi_dout, + i_dmi_req = self.dmi_req, + i_dmi_wr = self.dmi_wr, + o_dmi_ack = self.dmi_ack, ) # add vhdl sources diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 09674ae6..50ab2a98 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -3,7 +3,7 @@ import os import argparse -from migen import Signal, FSM, If, Display, Finish +from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState) from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform @@ -41,39 +41,90 @@ class LibreSoCSim(SoCCore): self.submodules.crg = CRG(platform.request("sys_clk")) # Debug --------------------------------------------------------------- - if debug: - uptime = Signal(64) - self.sync += uptime.eq(uptime + 1) - self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack & - self.cpu.ibus.we, - Display("[%06x] iadr: %8x, s %01x w %016x", - uptime, - self.cpu.ibus.adr, - self.cpu.ibus.sel, - self.cpu.ibus.dat_w, - ) + if not debug: + return + + # setup running of DMI FSM + dmi_addr = Signal(3) + dmi_din = Signal(64) + dmi_wen = Signal(64) + dmi_dout = Signal(64) + dmi_req = Signal(1) + + uptime = Signal(64) + # increment counter, Stop after 100000 cycles + uptime = Signal(64) + self.sync += uptime.eq(uptime + 1) + self.sync += If(uptime == 100000, Finish()) + + dmifsm = FSM() + self.submodules += dmifsm + + # DMI FSM + dmifsm.act("START", + If(dmi_req & dmi_wen, + (self.cpu.dmi_addr.eq(dmi_addr), # DMI Addr + self.cpu.dmi_din.eq(dmi_din), # DMI in + self.cpu.dmi_req.eq(1), # DMI request + self.cpu.dmi_wr.eq(1), # DMI write + If(self.cpu.dmi_ack, + (NextState("IDLE"), + self.cpu.dmi_addr.eq(0), + self.cpu.dmi_din.eq(0), + self.cpu.dmi_req.eq(0), + self.cpu.dmi_wr.eq(0), + ) + ), + ), ) - self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack & - ~self.cpu.ibus.we, - Display("[%06x] iadr: %8x, s %01x r %016x", - uptime, - self.cpu.ibus.adr, - self.cpu.ibus.sel, - self.cpu.ibus.dat_r - ) + ) + + dmifsm.act("IDLE", + (NextValue(dmi_req, 0), + ) + ) + + # kick off a "stop" + self.comb += If(uptime == 0, + (dmi_addr.eq(0), # CTRL + dmi_din.eq(1<<0), # STOP + dmi_req.eq(1), + dmi_wen.eq(1), + ) + ) + + # monitor ibus write + self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack & + self.cpu.ibus.we, + Display("[%06x] iadr: %8x, s %01x w %016x", + uptime, + self.cpu.ibus.adr, + self.cpu.ibus.sel, + self.cpu.ibus.dat_w, + ) + ) + # monitor ibus read + self.sync += If(self.cpu.ibus.stb & self.cpu.ibus.ack & + ~self.cpu.ibus.we, + Display("[%06x] iadr: %8x, s %01x r %016x", + uptime, + self.cpu.ibus.adr, + self.cpu.ibus.sel, + self.cpu.ibus.dat_r ) - self.sync += If(self.cpu.dbus.stb & self.cpu.dbus.ack, - Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x", - uptime, - self.cpu.dbus.adr, - self.cpu.dbus.we, - self.cpu.dbus.sel, - self.cpu.dbus.dat_w, - self.cpu.dbus.dat_r - ) + ) + + # monitor bbus read/write + self.sync += If(self.cpu.dbus.stb & self.cpu.dbus.ack, + Display("[%06x] dadr: %8x, we %d s %01x w %016x r: %016x", + uptime, + self.cpu.dbus.adr, + self.cpu.dbus.we, + self.cpu.dbus.sel, + self.cpu.dbus.dat_w, + self.cpu.dbus.dat_r ) - # Stop after 20000 cycles - self.sync += If(uptime == 100000, Finish()) + ) # Build ----------------------------------------------------------------------- -- 2.30.2