From 9199451c1535d3d36da16dbb279787a1d9619d24 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 30 Dec 2020 17:01:16 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 7acc0d3b7..34c263c10 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -161,7 +161,7 @@ there is no separate Vector register file*: it's all the same instruction, on the standard register file, just with a loop. Scalar happens to set that loop size to one. -Also, it is important to note from the above that, strictly speaking, Simple-V is not really a Vectorisation scheme at all: it is more of a hardware instruction "Compression scheme", allowing as it does for what would normally require multiple sequential instructions to be replaced with just one. This is where the rule that Program Order must be preserved in Sub-OC execution derives from. However in other ways, which will emerge below, the "tagging" concept presents an opportunity to include features definitely not common outside of Vector ISAs, and in that regard it's definitely a xlass of Vectorisation. +The important insight from the above is that, strictly speaking, Simple-V is not really a Vectorisation scheme at all: it is more of a hardware ISA "Compression scheme", allowing as it does for what would normally require multiple sequential instructions to be replaced with just one. This is where the rule that Program Order must be preserved in Sub-OC execution derives from. However in other ways, which will emerge below, the "tagging" concept presents an opportunity to include features definitely not common outside of Vector ISAs, and in that regard it's definitely a xlass of Vectorisation. ## Register "tagging" -- 2.30.2