From 919e7a22a13e276d9586299cc8d7d973e6690d90 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 Oct 2021 18:34:33 +0100 Subject: [PATCH] whitespace --- SEP-210803722-Libre-SOC-8-core.mdwn | 52 ++++++++++++++--------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn index 7a7880bcf..127249c55 100644 --- a/SEP-210803722-Libre-SOC-8-core.mdwn +++ b/SEP-210803722-Libre-SOC-8-core.mdwn @@ -111,7 +111,7 @@ Grant numbers: * Sorbonne Université: 163 FP7 projects and 195 H2020 projects -## 1.2 Methodology +## 1.2 Methodology * Everything that Libre-SOC does is published as Libre/Open Information at https://libre-soc.org/ - source code (https://git.libre-soc.org) is open and available under the LGPLv3+ License and other appropriate Libre/Open Licenses. @@ -121,10 +121,10 @@ Grant numbers: * Symbiyosys and its subcomponents for Formal Correctness Proofs are Libre/Open https://symbiyosys.readthedocs.io/. * GPS GNSS-SDR is also Open Source https://gnss-sdr.org/ and can be adapted for HELIX's requirement * Chips4Makers FlexLib is also Open Source https://gitlab.com/Chips4Makers but the NDA'd "ports" are not. -* To solve the above problem, all Libre/Open Developers will work with an Academic "Ghost" version, called C4M-FreePDK45 https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45. This "ghost" version will allow full (parallel-track) collaboration between Libre/Open Developers and those Participants creating "real" GDS-II Files, without violating Foundry NDAs. +* To solve the above problem, all Libre/Open Developers will work with an Academic "Ghost" version, called C4M-FreePDK45 https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45. This "ghost" version will allow full (parallel-track) collaboration between Libre/Open Developers and those Participants creating "real" GDS-II Files, without violating Foundry NDAs. -This methodology is based on an established process that has already allowed us to deliver demonstrable software and hardware results, the manifestation of which is our 180nm architecture test chip now in manufacture. This has involved a significant amount of cooperative development among the applicants, and others beyond, and the development of core supporting technology that this grant application can now efficiently build upon. +This methodology is based on an established process that has already allowed us to deliver demonstrable software and hardware results, the manifestation of which is our 180nm architecture test chip now in manufacture. This has involved a significant amount of cooperative development among the applicants, and others beyond, and the development of core supporting technology that this grant application can now efficiently build upon. We refer to other supporting technology sources further in this application and whilst they are not the core team they will critically contribute to the overall success. In particular, these groups can be supported by NLnet, whose "Works for the Public Good" remit is 100% compatible with the full transparency objectives (that the project's participants are already committed to) which will help by providing additional non-core-team development on an on-demand basis, on the back of NLnet's already-trusted commitment to fulfil European Union objectives under Grant Agreements No 825310 and 825322. @@ -148,7 +148,7 @@ Part of that involves Peter Hsu's cavatools (another NLnet Grant) which is (at p ## 2.1 Project’s pathways towards impact -The core of modern computing is the capability of the computational element of the systems and the microprocessors they are based around. Every twenty years there has been a significant evolutionary step in the technical concepts employed by these microprocessor devices. For example the last big step was the concept of RISC (Reduced Instruction Set) processors. These developments have been driven by many forces from cost of devices to limitations of the available technology of the time. +The core of modern computing is the capability of the computational element of the systems and the microprocessors they are based around. Every twenty years there has been a significant evolutionary step in the technical concepts employed by these microprocessor devices. For example the last big step was the concept of RISC (Reduced Instruction Set) processors. These developments have been driven by many forces from cost of devices to limitations of the available technology of the time. The Libre-SOC core is capable of becoming the next significant step change in microprocessor speed, technology, and reduction in equivalent computational power (Watts). @@ -172,7 +172,7 @@ The end-result here is, if deployed in mass-volume products world-wide including As the Libre-SOC core is the result of a Libre/Open Source project by default all of our development work has been published for the last four years. This was also a requirement of our EU funding through NLnet. In addition we have undertaken a full program of conference presentations, technology awareness activities and cooperation with key bodies such as the OpenPOWER Foundation and OpenPOWER Members (Libre-SOC is participating in a world-wide Open University Course about the OpenPOWER ISA, an activity led by IBM). Examples: -* https://openpowerfoundation.org/events/openpower-summit-2020-north-america/ +* https://openpowerfoundation.org/events/openpower-summit-2020-north-america/ * https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/ @@ -188,7 +188,7 @@ The Libre-SOC bugtracker (where we track our TODO actions) is public access (htt These are ongoing activities that actively encourage world-wide Open Participation, and shall remain so indefinitely. We will continue to grow these activities along with a commercial thread of publicity by RED Semiconductor Ltd to publicise and determine product family opportunities where RED Semiconductor Ltd will focus on potential product and market development built upon the Libre-SOC core technology. -## 2.3 Summary +## 2.3 Summary ### Specific needs @@ -203,7 +203,7 @@ In practical terms: as indicated in sections above there have been a number of s Not only that, but all of the ubiquitous Computing products (Apple, Intel, IBM, NVidia, AMD being the most well-known) are 100% non-EU-based. As far as EU Digital Sovereignty is concerned, this is an extremely serious and alarming situation, compounded by critical Foundries and know-how to run those Foundries also not being part of a Sovereign European remit. -If that was not enough, Foundries and the Semiconductor Industry requires NDAs that at the minimum prohibit full publication of Academic results, stifling innovation and research, in turn driving up the cost for EU businesses of the cost of ASIC products by creating artificial cost, overhead and knowledge barriers. +If that was not enough, Foundries and the Semiconductor Industry requires NDAs that at the minimum prohibit full publication of Academic results, stifling innovation and research, in turn driving up the cost for EU businesses of the cost of ASIC products by creating artificial cost, overhead and knowledge barriers. The entire Computing and Semiconductor Industry needs a new approach. @@ -333,7 +333,7 @@ In the case of the Participants, if we need "reserve" budgets for unforseen acti ### Target groups -Due to our Open real time publishing of the Libre-SOC project, our work can be forked by anyone at any time as a starting point or as a building block for new projects, potentially taking the ideas and concepts in any direction. These can be individuals or teams and they can be academics or industrialists, the point being that if we trigger a step change in the technology everyone should be able to benefit. +Due to our Open real time publishing of the Libre-SOC project, our work can be forked by anyone at any time as a starting point or as a building block for new projects, potentially taking the ideas and concepts in any direction. These can be individuals or teams and they can be academics or industrialists, the point being that if we trigger a step change in the technology everyone should be able to benefit. This is in addition to our own commercialisation plans. @@ -345,7 +345,7 @@ Open Source methodology leads to Open standards which leads to Open understandin ### Outcomes -As the development chain includes elements of commercialisation, beyond the immediate benefit to similar projects by the enhancement of the Libre/Open Source tool chain and the educational uplift provided directly and by example to other groups and European businesses and Educational Establishments planning Software-to-Silicon projects, the most direct outcome will be the availability, as devices in the market through RED Semiconductor Ltd, of a new concept in supercomputing power that is also completely security auditable and transparent. +As the development chain includes elements of commercialisation, beyond the immediate benefit to similar projects by the enhancement of the Libre/Open Source tool chain and the educational uplift provided directly and by example to other groups and European businesses and Educational Establishments planning Software-to-Silicon projects, the most direct outcome will be the availability, as devices in the market through RED Semiconductor Ltd, of a new concept in supercomputing power that is also completely security auditable and transparent. We are already aware of a commercial venture formed recently, who are aware and already benefiting from our work over the last three years to improve the Software-to-Silicon toolchain, that is now focusing on the finessing of the toolchain and its human interface to widen access to the methodology and IMEC are using our architectural test chip, currently in production, to validate and test their new cloud based chip design suite. The outcomes are already happening and are bound to magnify. @@ -385,7 +385,7 @@ Work Packages: # 3.1 Work plan and resources - + @@ -435,7 +435,7 @@ To manage the people who put in supplementary (by timescale) proposals intended https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/opportunities/topic-details/horizon-cl4-2021-digital-emerging-01-01 -This will allow us to address and deploy new ideas and concepts not immediately available to us at the time of this submission, and have them properly vetted by an Organisation both familiar with our work, and already trusted by the EU to fulfil the same role for other EU Grants. +This will allow us to address and deploy new ideas and concepts not immediately available to us at the time of this submission, and have them properly vetted by an Organisation both familiar with our work, and already trusted by the EU to fulfil the same role for other EU Grants. Description of work: @@ -548,7 +548,7 @@ Deliverables: * 3.1. Delivery of an updated version of cavatools with new Draft SVP64 features * 3.2. Delivery of a version of cavatools with hardware-accurate models including Out-of-Order Execution * 3.3. Delivery of additional co-simulation and co-execution options to the Libre-SOC "Test API" including at least IBM POWER 9 (and POWER 10 if access can be obtained), and Microwatt. -* 3.4. Delivery of an implementation of a Compliance Test Suite that meets the OpenPOWER Foundation's criteria +* 3.4. Delivery of an implementation of a Compliance Test Suite that meets the OpenPOWER Foundation's criteria * 3.5. Delivery of the documentation and an implementation of a Compliance Test Suite for Draft SVP64 Extensions for submission to the relevant OpenPOWER Foundation Workgroup. * 3.6. Public reports on all of the above at Conferences and on the Libre-SOC website. @@ -589,7 +589,7 @@ Description of work: Deliverables: -* 4.1. Feasibility report on the viability and scope of achievable work within the available respective budgets for each deliverable +* 4.1. Feasibility report on the viability and scope of achievable work within the available respective budgets for each deliverable * 4.2. Prototype compilers for each of gcc, llvm, Kazan and MESA3D meeting the scope of achievable work defined in the Feasibility study, delivered in source code form under appropriate Libre-Licenses and including unit test bench source code demonstrating successfully meeting the objectives * 4.3. Prototype ports of libc6, u-boot, Linux Kernel and other software demonstrated to meet the scope of achievable work, delivered in source code form under appropriate Libre-Licenses with unit tests. * 4.4. Public reports on the above and presentations at suitable Conferences @@ -840,7 +840,7 @@ Description of work: Please Note: Work Packages 7, 8 and 9 are highly interdependent and will cross fertilise their results in an iterative manner as the design complexity increases, starting from smaller rapid-prototype test ASIC layouts and progressing to full designs. -* To create VLSI Layouts using Libre-SOC HDL +* To create VLSI Layouts using Libre-SOC HDL * To prepare and submit GDS-II Files to IMEC under appropriate MPW Shuttle Runs * To develop a Test jig, including custom test socket and supporting test software for each ASIC and to produce an appropriate report * To publish Academic Papers and other materials, on websites and at Conferences, on the results of each Tape-out. @@ -940,9 +940,9 @@ Deliverables: ## Table 3.1c List of Deliverables - + Essential deliverables for effective project monitoring. - + |Deliv. #|Deliverable name |Wp # | Lead name |Type |Diss. |Del Mon | |------ |----------- |------ | ------- |------ |----------- | ---- | |1.3 |Reports |1 |5/NLnet |R |PU |12/24/36 | @@ -966,7 +966,7 @@ Essential deliverables for effective project monitoring. |11.2 |Requirements |11 |6/HELIX |R |PU |12 | |11.5 |Reporting |11 |6/HELIX |R |PU |12/24/36 | -## Table 3.1d: List of milestones +## Table 3.1d: List of milestones |M/stone #|Milestone name |WP# |Due date |Means of verification | @@ -1019,7 +1019,7 @@ Risk level: (i) likelihood L/M/H,(ii) severity: Low/Medium/High ## 3.1g Subcontracting -### Table 3.1g: 1/RED ‘Subcontracting costs’ items +### Table 3.1g: 1/RED ‘Subcontracting costs’ items |Cost EUR |description and justification | @@ -1035,7 +1035,7 @@ Risk level: (i) likelihood L/M/H,(ii) severity: Low/Medium/High |4790000 | total | -### Table 3.1g: 5/NLnet ‘Subcontracting / Sub-Grant costs’ items +### Table 3.1g: 5/NLnet ‘Subcontracting / Sub-Grant costs’ items |Cost EUR |description and justification | @@ -1082,7 +1082,7 @@ Risk level: (i) likelihood L/M/H,(ii) severity: Low/Medium/High |Total | | | -### Table 3.1h: 5/NLnet +### Table 3.1h: 5/NLnet | |Cost EUR |Justification | @@ -1097,16 +1097,16 @@ Risk level: (i) likelihood L/M/H,(ii) severity: Low/Medium/High # 3.2 Capacity of participants and consortium as a whole -The majority of the consortium have been working together for over three years on the precursor technical development of the Libre-SOC core project, the evolution of which is the lynch-pin and "proving-ground" of this grant application. The public record of their achievements and team involvement can be found in their public Open Source record https://libre-soc.org/. +The majority of the consortium have been working together for over three years on the precursor technical development of the Libre-SOC core project, the evolution of which is the lynch-pin and "proving-ground" of this grant application. The public record of their achievements and team involvement can be found in their public Open Source record https://libre-soc.org/. The Libre-SOC team are internationally experienced software professionals who have strong familiarity with state of the art software to silicon technologies. They have been supported by two of the co-applicants labs CNRS and LIP6 (The applicants being Sorbonne Université and Affiliated Entity, CNRS), and many other European based technology development groups, which each provide key elements of the project from specialist programs such as coriolis2, alliance, HITAS, YAGLE and more, and the manufacturing expertise of Imec. Their versatility and experience with Libre/Open Source Software also means that they can adapt to unforeseen circumstances and can navigate the ever-changing and constantly-evolving FOSS landscape with confidence. The above is critically important in light of the requirement to demonstrate access to critical infrastructure, resources and the ability to fulfil: with the sole exception of NDA'd Foundry PDKs (Physical Design Kits), the entirety of this project is Libre/Open Source, both in the tools it utilises, components that it uses, and the results that are generated. With there being no restriction on the availability of Libre/Open Source software needed to complete the project, the Participants correspondingly have no impediment. We also have a proven strategy to deal with the NDA's: a "parallel track" where at least one Participant (Sorbonne Université, LIP6 Lab) has signed TSMC Foundry NDAs, and consequently there is no impediment there, either. Sorbonne Université (SU) is a multidisciplinary, research-intensive and world class academic institution. It was created on January 1st 2018 as the merger of two first-class research intensive universities, UPMC (University Pierre and Marie Curie) and Paris-Sorbonne. Sorbonne Université is now organized with three faculties: humanities, medicine and science each with the wide-ranging autonomy necessary to conduct its ambitious programs in both research and education. SU counts 53,500 students, 3,400 professor-researchers and 3,600 administrative and technical staff members. SU is intensively engaged in European research projects (163 FP7 projects and 195 H2020 projects). -Its computer science laboratory, LIP6, is internationally recognized as a leading research institute. +Its computer science laboratory, LIP6, is internationally recognized as a leading research institute. -LIP6 is a Joint Research Unit of both SU (Sorbonne Université) and CNRS. Both entities invest resources within LIP6 so CNRS is then an Affiliated Entity linked to SU. According to SU-CNRS agreement regarding LIP6, SU, as a full partner, manages the grant for its Affiliated Entity, CNRS. +LIP6 is a Joint Research Unit of both SU (Sorbonne Université) and CNRS. Both entities invest resources within LIP6 so CNRS is then an Affiliated Entity linked to SU. According to SU-CNRS agreement regarding LIP6, SU, as a full partner, manages the grant for its Affiliated Entity, CNRS. RED Semiconductor Ltd has been established as a commercialisation vehicle, sharing the Libre principles of the core Libre-SOC team and bringing Semiconductor industry commercial management and technology experience. This includes the founders of two successful semiconductor companies and a public company chairman. There is also a cross directorship of Luke Leighton (of Libre-SOC) giving the company an extensive technology market and leadership experience. @@ -1120,12 +1120,12 @@ Regarding the extreme high-end computing resources necessary to complete the exc We have established that Embecosm Gmbh and Vrull.eu are some of the world's leading experts in Compiler Technology. We will put out to tender a Contract with an initial evaluation phase, followed by a TRL 4/5 Research phase for the prerequisite compilers (gcc, llvm, Kazan, MESA3D) necessary to support the core design work. -The OpenPOWER Foundation is a part of the Linux Foundation, and is directly responsible for the long-term protection and evolution of the Power ISA. Members include IBM, Google, NVidia, Raptor Engineering, University of Oregon and many more. -https://openpowerfoundation.org/membership/current-members/. +The OpenPOWER Foundation is a part of the Linux Foundation, and is directly responsible for the long-term protection and evolution of the Power ISA. Members include IBM, Google, NVidia, Raptor Engineering, University of Oregon and many more. +https://openpowerfoundation.org/membership/current-members/. The Chair of the newly-formed ISA Working Group is Paul Mackerras, and the Technical Chair is Toshaan Bharvani. Both of these people have been kindly attending bi-weekly meetings with the Libre-SOC Team for over 18 months, and we have kept them apprised of ongoing developments, particularly with the Draft SVP64 ISA Extension. They are both going out of their way to regularly advise us on how to go about a successful RFC Process for SVP64, and we deeply appreciate their support. -HELIX Technology's involvement, as a potential customer and potential user of the Libre-SOC technology, will give focus to the deliverable of the project. They have world-leading expertise in Antenna Technology, and in the mathematics behind the Signal Processing required for GNSS/GPS. We have deliberately selected them to ensure the ambition of our overall project. +HELIX Technology's involvement, as a potential customer and potential user of the Libre-SOC technology, will give focus to the deliverable of the project. They have world-leading expertise in Antenna Technology, and in the mathematics behind the Signal Processing required for GNSS/GPS. We have deliberately selected them to ensure the ambition of our overall project. We therefore have a cohesive cooperative team of experience from concept to customer product and a supporting cast of specialist technical support that are an established practiced team. -- 2.30.2