From 91ab3f0d01d6c36c4ef180e7e6826b7fd44e67d6 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 10 Sep 2015 13:56:56 -0700
Subject: [PATCH] remove genlib.misc.optree (use reduce instead)

---
 examples/basic/namer.py |  6 ++++--
 examples/sim/fir.py     |  5 +++--
 migen/genlib/misc.py    | 21 ---------------------
 migen/genlib/record.py  |  9 ++++++---
 4 files changed, 13 insertions(+), 28 deletions(-)

diff --git a/examples/basic/namer.py b/examples/basic/namer.py
index 0983520e..670de37e 100644
--- a/examples/basic/namer.py
+++ b/examples/basic/namer.py
@@ -1,6 +1,8 @@
 from migen.fhdl.std import *
 from migen.fhdl import verilog
-from migen.genlib.misc import optree
+
+from functools import reduce
+from operator import or_
 
 
 def gen_list(n):
@@ -37,6 +39,6 @@ class Example(Module):
         for lst in [a, b, c]:
             for obj in lst:
                 allsigs.extend(obj.sigs)
-        self.comb += output.eq(optree("|", allsigs))
+        self.comb += output.eq(reduce(or_, allsigs))
 
 print(verilog.convert(Example()))
diff --git a/examples/sim/fir.py b/examples/sim/fir.py
index e31cc144..641f6b38 100644
--- a/examples/sim/fir.py
+++ b/examples/sim/fir.py
@@ -4,9 +4,10 @@ import matplotlib.pyplot as plt
 
 from migen.fhdl.std import *
 from migen.fhdl import verilog
-from migen.genlib.misc import optree
 from migen.sim.generic import run_simulation
 
+from functools import reduce
+from operator import add
 
 # A synthesizable FIR filter.
 class FIR(Module):
@@ -27,7 +28,7 @@ class FIR(Module):
             c_fp = int(c*2**(self.wsize - 1))
             muls.append(c_fp*sreg)
         sum_full = Signal((2*self.wsize-1, True))
-        self.sync += sum_full.eq(optree("+", muls))
+        self.sync += sum_full.eq(reduce(add, muls))
         self.comb += self.o.eq(sum_full[self.wsize-1:])
 
 
diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
index bd782863..aa610da3 100644
--- a/migen/genlib/misc.py
+++ b/migen/genlib/misc.py
@@ -1,25 +1,4 @@
 from migen.fhdl.std import *
-from migen.fhdl.structure import _Operator
-
-
-def optree(op, operands, lb=None, ub=None, default=None):
-    if lb is None:
-        lb = 0
-    if ub is None:
-        ub = len(operands)
-    l = ub - lb
-    if l == 0:
-        if default is None:
-            raise AttributeError
-        else:
-            return default
-    elif l == 1:
-        return operands[lb]
-    else:
-        s = lb + l//2
-        return _Operator(op,
-            [optree(op, operands, lb, s, default),
-            optree(op, operands, s, ub, default)])
 
 
 def split(v, *counts):
diff --git a/migen/genlib/record.py b/migen/genlib/record.py
index 05151bc6..238c9140 100644
--- a/migen/genlib/record.py
+++ b/migen/genlib/record.py
@@ -1,6 +1,9 @@
 from migen.fhdl.std import *
 from migen.fhdl.tracer import get_obj_var_name
-from migen.genlib.misc import optree
+
+from functools import reduce
+from operator import or_
+
 
 (DIR_NONE, DIR_S_TO_M, DIR_M_TO_S) = range(3)
 
@@ -141,7 +144,7 @@ class Record:
                     if direction == DIR_M_TO_S:
                         r += [getattr(slave, field).eq(self_e) for slave in slaves]
                     elif direction == DIR_S_TO_M:
-                        r.append(self_e.eq(optree("|", [getattr(slave, field) for slave in slaves])))
+                        r.append(self_e.eq(reduce(or_, [getattr(slave, field) for slave in slaves])))
                     else:
                         raise TypeError
                 else:
@@ -164,7 +167,7 @@ class Record:
                     s_signal, s_direction = next(iter_slave)
                     assert(s_direction == DIR_S_TO_M)
                     s_signals.append(s_signal)
-                r.append(m_signal.eq(optree("|", s_signals)))
+                r.append(m_signal.eq(reduce(or_, s_signals)))
             else:
                 raise TypeError
         return r
-- 
2.30.2