From 91d585c8418acf005576dff0d6b0904be281ccd0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 16:10:28 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 91789bab2..7bc8da50f 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -186,7 +186,7 @@ These are the modes: * **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results. * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria. * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. -* **reduce mode**. when M=1 a mapreduce is performed. the result is a scalar. a vector however is required, as it may be used to store intermediary computations. the result is in the first element with a nonzero predicate bit. +* **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see separate section below. note that reduce mode only applies to 2 src operations. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). -- 2.30.2