From 9207ea92ed1826263728f5c28f952656de5c0b16 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 20 Dec 2020 22:00:14 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64.mdwn | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index d00bb8305..ccef9b21b 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -33,7 +33,9 @@ Note that this is completely different from when VL=0.  VL=0 turns all operation
 # Register Naming
 
 SV Registers are simply the INT, FP and CR register files extended
-linearly to larger sizes.  Where the integer regfile in standard scalar
+linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
+
+Where the integer regfile in standard scalar
 OpenPOWER v3.0B and v3.1B is r0 to r31, SV extends this as r0 to r127.
 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
 extended to 64 entries, CR0 thru CR63.
-- 
2.30.2