From 921ef4aa0cbcc5bf15f73ce0dbc74e597912273e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 9 May 2023 00:31:00 -0700 Subject: [PATCH] access XER via fields --- openpower/isa/av.mdwn | 12 ++++++------ openpower/isa/comparefixed.mdwn | 8 ++++---- openpower/isa/sprset.mdwn | 2 +- src/openpower/decoder/isa/caller.py | 5 ++++- 4 files changed, 15 insertions(+), 12 deletions(-) diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn index 94c3e1c8..77cb6c26 100644 --- a/openpower/isa/av.mdwn +++ b/openpower/isa/av.mdwn @@ -25,11 +25,11 @@ Pseudo-code: # if Rc = 1 then store the result of comparing a and b to CR0 if Rc = 1 then if a u b then - CR0 <- 0b010 || XER[SO] + CR0 <- 0b010 || XER.SO if MMM[2] then # max mode # swap a and b to make the less than comparison do # greater than comparison of the original inputs @@ -68,11 +68,11 @@ Pseudo-code: # if Rc = 1 then store the result of comparing a and b to CR0 # if Rc = 1 then # if a u b then - # CR0 <- 0b010 || XER[SO] + # CR0 <- 0b010 || XER.SO if MMM[2] then # max mode # swap a and b to make the less than comparison do # greater than comparison of the original inputs diff --git a/openpower/isa/comparefixed.mdwn b/openpower/isa/comparefixed.mdwn index af92870a..a19e638c 100644 --- a/openpower/isa/comparefixed.mdwn +++ b/openpower/isa/comparefixed.mdwn @@ -20,7 +20,7 @@ Pseudo-code: if a < EXTS(SI) then c <- 0b100 else if a > EXTS(SI) then c <- 0b010 else c <- 0b001 - CR[4*BF+32:4*BF+35] <- c || XER[SO] + CR[4*BF+32:4*BF+35] <- c || XER.SO Special Registers Altered: @@ -43,7 +43,7 @@ Pseudo-code: if a < b then c <- 0b100 else if a > b then c <- 0b010 else c <- 0b001 - CR[4*BF+32:4*BF+35] <- c || XER[SO] + CR[4*BF+32:4*BF+35] <- c || XER.SO Special Registers Altered: @@ -62,7 +62,7 @@ Pseudo-code: if a u ([0]*(XLEN-16) || UI) then c <- 0b010 else c <- 0b001 - CR[4*BF+32:4*BF+35] <- c || XER[SO] + CR[4*BF+32:4*BF+35] <- c || XER.SO Special Registers Altered: @@ -85,7 +85,7 @@ Pseudo-code: if a u b then c <- 0b010 else c <- 0b001 - CR[4*BF+32:4*BF+35] <- c || XER[SO] + CR[4*BF+32:4*BF+35] <- c || XER.SO Special Registers Altered: diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn index f51cbbb6..bb8a8c5d 100644 --- a/openpower/isa/sprset.mdwn +++ b/openpower/isa/sprset.mdwn @@ -83,7 +83,7 @@ X-Form Pseudo-code: - CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32] + CR[4*BF+32:4*BF+35] <- XER.OV || XER.OV32 || XER.CA || XER.CA32 Special Registers Altered: diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index f1e9d6ee..7671bc67 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -39,6 +39,7 @@ from openpower.decoder.power_svp64 import SVP64RM, decode_extra from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) from openpower.fpscr import FPSCRState +from openpower.xer import XERState from openpower.util import LogKind, log instruction_info = namedtuple('instruction_info', @@ -266,7 +267,7 @@ class SPR(dict): info = spr_dict[key] else: info = spr_byname[key] - dict.__setitem__(self, key, SelectableInt(0, info.length)) + self[key] = SelectableInt(0, info.length) res = dict.__getitem__(self, key) log("spr returning", key, res) return res @@ -282,6 +283,8 @@ class SPR(dict): self.__setitem__('SRR0', value) if key == 'HSRR1': # HACK! self.__setitem__('SRR1', value) + if key == 1: + value = XERState(value) log("setting spr", key, value) dict.__setitem__(self, key, value) -- 2.30.2