From 922f9c255896c0e24e997292cc7518b4b6545e7c Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 8 Sep 2015 19:08:34 +0000 Subject: [PATCH] [AArch64] Implement vcvt_{,high_}f16_f32 * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf): Reparameterize to... (aarch64_float_truncate_lo_): ...this, for both V2SF and V4HF. (aarch64_float_truncate_hi_v4sf): Reparameterize to... (aarch64_float_truncate_hi_): ...this, for both V4SF and V8HF. * config/aarch64/aarch64-simd-builtins.def (float_truncate_hi_): Add v8hf variant. (float_truncate_lo_): Use BUILTIN_VDF iterator. * config/aarch64/arm_neon.h (vcvt_f16_f32, vcvt_high_f16_f32): New. * config/aarch64/iterators.md (VDF, Vdtype): New. (VWIDE, Vmwtype): Add cases for V4HF and V2SF. From-SVN: r227545 --- gcc/ChangeLog | 17 ++++++++++++++ gcc/config/aarch64/aarch64-simd-builtins.def | 3 ++- gcc/config/aarch64/aarch64-simd.md | 24 ++++++++++---------- gcc/config/aarch64/arm_neon.h | 16 +++++++++---- gcc/config/aarch64/iterators.md | 10 +++++++- 5 files changed, 52 insertions(+), 18 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a4e8d0f4db..4f267d23bc2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2015-09-08 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf): + Reparameterize to... + (aarch64_float_truncate_lo_): ...this, for both V2SF and V4HF. + (aarch64_float_truncate_hi_v4sf): Reparameterize to... + (aarch64_float_truncate_hi_): ...this, for both V4SF and V8HF. + + * config/aarch64/aarch64-simd-builtins.def (float_truncate_hi_): Add + v8hf variant. + (float_truncate_lo_): Use BUILTIN_VDF iterator. + + * config/aarch64/arm_neon.h (vcvt_f16_f32, vcvt_high_f16_f32): New. + + * config/aarch64/iterators.md (VDF, Vdtype): New. + (VWIDE, Vmwtype): Add cases for V4HF and V2SF. + 2015-09-08 Alan Lawrence * config/aarch64/aarch64.c (aarch64_split_simd_combine): Add V4HFmode. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 39ff34e16d8..c5b46aa1404 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -363,9 +363,10 @@ VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) VAR1 (BINOP, float_truncate_hi_, 0, v4sf) + VAR1 (BINOP, float_truncate_hi_, 0, v8hf) VAR1 (UNOP, float_extend_lo_, 0, v2df) - VAR1 (UNOP, float_truncate_lo_, 0, v2sf) + BUILTIN_VDF (UNOP, float_truncate_lo_, 0) /* Implemented by aarch64_ld1. */ BUILTIN_VALL_F16 (LOAD1, ld1, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 1bd6a19aea0..8bd4057c808 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1726,23 +1726,23 @@ ;; Float narrowing operations. -(define_insn "aarch64_float_truncate_lo_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=w") - (float_truncate:V2SF - (match_operand:V2DF 1 "register_operand" "w")))] +(define_insn "aarch64_float_truncate_lo_" + [(set (match_operand:VDF 0 "register_operand" "=w") + (float_truncate:VDF + (match_operand: 1 "register_operand" "w")))] "TARGET_SIMD" - "fcvtn\\t%0.2s, %1.2d" + "fcvtn\\t%0., %1" [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) -(define_insn "aarch64_float_truncate_hi_v4sf" - [(set (match_operand:V4SF 0 "register_operand" "=w") - (vec_concat:V4SF - (match_operand:V2SF 1 "register_operand" "0") - (float_truncate:V2SF - (match_operand:V2DF 2 "register_operand" "w"))))] +(define_insn "aarch64_float_truncate_hi_" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand:VDF 1 "register_operand" "0") + (float_truncate:VDF + (match_operand: 2 "register_operand" "w"))))] "TARGET_SIMD" - "fcvtn2\\t%0.4s, %2.2d" + "fcvtn2\\t%0., %2" [(set_attr "type" "neon_fp_cvt_narrow_d_q")] ) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 2bb75bb0eba..02e9af2d0e7 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5725,12 +5725,8 @@ vaddlvq_u32 (uint32x4_t a) result; \ }) -/* vcvt_f16_f32 not supported */ - /* vcvt_f32_f16 not supported */ -/* vcvt_high_f16_f32 not supported */ - /* vcvt_high_f32_f16 not supported */ #define vcvt_n_f32_s32(a, b) \ @@ -13114,6 +13110,18 @@ vcntq_u8 (uint8x16_t __a) /* vcvt (double -> float). */ +__extension__ static __inline float16x4_t __attribute__ ((__always_inline__)) +vcvt_f16_f32 (float32x4_t __a) +{ + return __builtin_aarch64_float_truncate_lo_v4hf (__a); +} + +__extension__ static __inline float16x8_t __attribute__ ((__always_inline__)) +vcvt_high_f16_f32 (float16x4_t __a, float32x4_t __b) +{ + return __builtin_aarch64_float_truncate_hi_v8hf (__a, __b); +} + __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vcvt_f32_f64 (float64x2_t __a) { diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 58cc0008549..d7dfdc1ff25 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -41,6 +41,9 @@ ;; Iterator for General Purpose Float registers, inc __fp16. (define_mode_iterator GPF_F16 [HF SF DF]) +;; Double vector modes. +(define_mode_iterator VDF [V2SF V4HF]) + ;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) @@ -449,6 +452,9 @@ (SI "V2SI") (DI "V2DI") (DF "V2DF")]) +;; Register suffix for double-length mode. +(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) + ;; Double modes of vector modes (lower case). (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") (V4HF "v8hf") @@ -482,7 +488,8 @@ (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI") (V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") - (HI "SI") (SI "DI")] + (HI "SI") (SI "DI") + (V4HF "V4SF") (V2SF "V2DF")] ) @@ -495,6 +502,7 @@ (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") (V2SI ".2d") (V16QI ".8h") (V8HI ".4s") (V4SI ".2d") + (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) ;; Lower part register suffixes for VQW. -- 2.30.2