From 923f907f6b5919ac1b97028a92f4279ed91024ee Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Feb 2022 10:54:11 +0000
Subject: [PATCH] xdr=4 missing on ddr3 platform request for VERSA_ECP5

---
 src/ls2.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/ls2.py b/src/ls2.py
index dcdc0de..4197bec 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -357,7 +357,8 @@ if __name__ == "__main__":
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"clk":4, "a":4, "ba":4, "clk_en":4,
-                                         "odt":4, "ras":4, "cas":4, "we":4})
+                                         "odt":4, "ras":4, "cas":4, "we":4,
+                                         "cs": 4})
 
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
-- 
2.30.2