From 92649a3e6756465b3961cf05910cda93a69c7790 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 12 Apr 2017 16:54:49 -0700 Subject: [PATCH] i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit On IVB, DF instructions have lowered the SIMD width to 4 but the exec_size will be later doubled. Fix the assert to avoid crashing in this case. Signed-off-by: Samuel Iglesias Gonsálvez [ Francisco Jerez: Simplify assert. Except for the 'inst->group % 4 == 0' part the assertion was redundant with the previous assertion. ] Reviewed-by: Francisco Jerez --- src/intel/compiler/brw_vec4_generator.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index 5be4ef7fd4b..09081588400 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1524,11 +1524,7 @@ generate_code(struct brw_codegen *p, brw_set_default_acc_write_control(p, inst->writes_accumulator); assert(inst->group % inst->exec_size == 0); - assert(inst->group % 8 == 0 || - inst->dst.type == BRW_REGISTER_TYPE_DF || - inst->src[0].type == BRW_REGISTER_TYPE_DF || - inst->src[1].type == BRW_REGISTER_TYPE_DF || - inst->src[2].type == BRW_REGISTER_TYPE_DF); + assert(inst->group % 4 == 0); unsigned exec_size = inst->exec_size; if (devinfo->gen == 7 && -- 2.30.2